MerryMage
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05e97058c3
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parallel: Add and Subtract with Exchange improvements
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
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2017-03-24 15:56:24 +00:00 |
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MerryMage
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48693eb6ff
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Implement coprocessor-related microinstructions
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
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2017-01-08 14:56:06 +00:00 |
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MerryMage
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1efd3a764d
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IR: Remove unused microinstructions NegateLowWord and NegateHighWord
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2017-01-05 20:16:39 +00:00 |
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FernandoS27
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d5610eb26c
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Implement UHASX, UHSAX, SHASX and SHSAX (#75)
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2016-12-28 21:32:22 +00:00 |
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Fernando Sahmkow
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677f62dd6f
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Implement SHSUB8 and SHSUB16 (#74)
* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
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2016-12-22 12:02:24 +00:00 |
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MerryMage
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6a269a6ebd
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IR: Add microinstructions UnsignedSaturation and SignedSaturation
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2016-12-21 19:51:25 +00:00 |
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FernandoS27
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8919265d2c
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Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
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2016-12-20 21:52:38 +00:00 |
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FernandoS27
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3f6ecfe245
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Implemented USAD8 and USADA8
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2016-12-20 21:52:38 +00:00 |
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MerryMage
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96e46ba6b5
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Implement QADD, QSUB, QDADD, QDSUB
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2016-12-15 22:34:29 +00:00 |
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MerryMage
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52e1445f43
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Implement USUB8
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2016-12-05 00:29:15 +00:00 |
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MerryMage
|
5c1aab1666
|
Implement CLZ
Includes tests
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2016-12-04 22:56:33 +00:00 |
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MerryMage
|
1a1646d962
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Implement UADD8
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2016-12-04 20:52:33 +00:00 |
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MerryMage
|
e166965f3e
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Implement VCMP
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2016-12-03 11:41:09 +00:00 |
|
MerryMage
|
f2fe376fc6
|
Support 64-bit immediates
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2016-12-03 11:29:50 +00:00 |
|
Merry
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0ff8c375af
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Implement UHSUB8 and UHSUB16 (#48)
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2016-11-26 18:27:21 +00:00 |
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Merry
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cb17f9a3ed
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Implement SHADD8 and SHADD16 (#47)
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2016-11-26 18:12:29 +00:00 |
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MerryMage
|
c0c1bb1094
|
Implemented UHADD16
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2016-11-26 11:28:20 +00:00 |
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Sebastian Valle
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4d44474ad4
|
Implemented the ARM UHADD8 instruction. (#45)
The x64 implementation uses the SSSE3 instruction PSHUFB.
A non-SSE fallback is provided in case the CPU doesn't support it.
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2016-11-25 20:32:22 +00:00 |
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MerryMage
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b6f7b8babd
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ir: Implement GetGEFlags, SetGEFlags
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2016-11-23 19:44:27 +00:00 |
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Mat M
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6d53bb6d7e
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arm_types: Split out LocationDescriptor (#20)
This isn't really an ARM-specific type, since it's used to indicate a
Block location.
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2016-09-05 11:54:09 +01:00 |
|
Mat M
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7f9a0c3c38
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Remove unnecessary explicit includes (#16)
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2016-09-03 21:48:03 +01:00 |
|
Mat M
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a465b2ddbc
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ir_emitter: Fix typo. ClearExlcusive -> ClearExclusive (#5)
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2016-09-02 12:17:22 +01:00 |
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MerryMage
|
dca3b2f079
|
Implement VMRS and VMSR
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2016-08-26 22:47:54 +01:00 |
|
MerryMage
|
30df51c2dc
|
ir_emitter: Should be in the IR namespace, not the Arm namespace
|
2016-08-25 17:36:42 +01:00 |
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MerryMage
|
b5a86889cd
|
Implement VCVT
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2016-08-23 22:20:04 +01:00 |
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Lioncash
|
841098a0bc
|
ir: separate components out a little more
|
2016-08-17 20:46:21 +01:00 |
|
MerryMage
|
e164ede4dc
|
TranslateArm: Implement MRS, MSR (imm), MSR (reg)
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2016-08-15 11:50:49 +01:00 |
|
MerryMage
|
960d14d18e
|
Optimization: Implement Return Stack Buffer
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2016-08-13 00:10:23 +01:00 |
|
bunnei
|
8e68e6fdd9
|
TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
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2016-08-12 19:00:44 +01:00 |
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bunnei
|
4b09c0d032
|
TranslateArm: Implement QADD8 and UQADD8.
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2016-08-12 19:00:44 +01:00 |
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bunnei
|
127fbe99cb
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TranslateArm: Implement QSUB8.
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2016-08-12 19:00:44 +01:00 |
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bunnei
|
86fe29c6d2
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TranslateArm: Implement UQSUB8.
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2016-08-12 19:00:44 +01:00 |
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MerryMage
|
1029fd27ce
|
Update documentation (2016-08-12)
|
2016-08-12 18:17:31 +01:00 |
|
MerryMage
|
df39308e03
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
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2016-08-09 22:57:20 +01:00 |
|
Tillmann Karras
|
5d26899ac9
|
Add simplified LogicalShiftRight64 IR opcode
|
2016-08-08 22:27:05 +01:00 |
|
Tillmann Karras
|
ccb2aa96a5
|
Add support for the APSR.Q flag
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2016-08-08 22:27:04 +01:00 |
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MerryMage
|
a2c2db277b
|
VFP: Implement VMOV (all variants)
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2016-08-07 19:25:12 +01:00 |
|
MerryMage
|
0f412247ed
|
VFP: Implement VSQRT
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2016-08-07 12:19:07 +01:00 |
|
MerryMage
|
3f1345a1a5
|
VFP: Implement VNMUL, VDIV
|
2016-08-07 10:56:12 +01:00 |
|
MerryMage
|
12e7f2c359
|
VFP: Implement VMUL
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2016-08-07 10:21:14 +01:00 |
|
MerryMage
|
97b5fa173f
|
VFP: Implement VSUB
|
2016-08-07 01:45:52 +01:00 |
|
MerryMage
|
ce6b5f8210
|
VFP: Implement VABS
|
2016-08-07 01:27:18 +01:00 |
|
Tillmann Karras
|
846d07d7b5
|
Add Sub64 opcode
|
2016-08-06 21:17:11 +01:00 |
|
Tillmann Karras
|
b9f4f1ed0f
|
Add carry support to MostSignificantWord
|
2016-08-06 21:17:11 +01:00 |
|
Tillmann Karras
|
01aebcb385
|
Remove *MulHi wrappers
|
2016-08-06 21:17:11 +01:00 |
|
MerryMage
|
4b31ea25a7
|
VFP: Implement VADD.{F32,F64}
|
2016-08-06 20:03:15 +01:00 |
|
MerryMage
|
640ce48baa
|
VFP: Implement {Get,Set}ExtendedRegister{32,64}
|
2016-08-05 19:06:10 +01:00 |
|
MerryMage
|
b4aa01ccf4
|
Merge remote-tracking branch 'tilkax/master'
|
2016-08-05 14:14:06 +01:00 |
|
MerryMage
|
ca40015145
|
IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
|
2016-08-05 14:07:27 +01:00 |
|
Tillmann Karras
|
3fdc093d10
|
Add more IR opcodes for multiply instructions
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
|
2016-08-05 02:09:30 +01:00 |
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