183 lines
7.9 KiB
C++
183 lines
7.9 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#pragma once
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#include <initializer_list>
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#include "common/common_types.h"
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#include "frontend/arm_types.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/opcodes.h"
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#include "frontend/ir/terminal.h"
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#include "frontend/ir/value.h"
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// ARM JIT Microinstruction Intermediate Representation
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//
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// This intermediate representation is an SSA IR. It is designed primarily for analysis,
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// though it can be lowered into a reduced form for interpretation. Each IR node (Value)
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// is a microinstruction of an idealised ARM CPU. The choice of microinstructions is made
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// not based on any existing microarchitecture but on ease of implementation.
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namespace Dynarmic {
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namespace IR {
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/**
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* Convenience class to construct a basic block of the intermediate representation.
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* `block` is the resulting block.
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* The user of this class updates `current_location` as appropriate.
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*/
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class IREmitter {
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public:
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explicit IREmitter(Arm::LocationDescriptor descriptor) : block(descriptor), current_location(descriptor) {}
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Block block;
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Arm::LocationDescriptor current_location;
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struct ResultAndCarry {
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Value result;
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Value carry;
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};
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struct ResultAndCarryAndOverflow {
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Value result;
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Value carry;
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Value overflow;
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};
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void Unimplemented();
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u32 PC();
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u32 AlignPC(size_t alignment);
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Value Imm1(bool value);
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Value Imm8(u8 value);
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Value Imm32(u32 value);
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Value GetRegister(Arm::Reg source_reg);
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Value GetExtendedRegister(Arm::ExtReg source_reg);
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void SetRegister(const Arm::Reg dest_reg, const Value& value);
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void SetExtendedRegister(const Arm::ExtReg dest_reg, const Value& value);
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void ALUWritePC(const Value& value);
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void BranchWritePC(const Value& value);
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void BXWritePC(const Value& value);
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void LoadWritePC(const Value& value);
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void CallSupervisor(const Value& value);
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void PushRSB(const Arm::LocationDescriptor& return_location);
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Value GetCpsr();
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void SetCpsr(const Value& value);
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Value GetCFlag();
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void SetNFlag(const Value& value);
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void SetZFlag(const Value& value);
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void SetCFlag(const Value& value);
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void SetVFlag(const Value& value);
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void OrQFlag(const Value& value);
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Value GetFpscr();
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void SetFpscr(const Value& new_fpscr);
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Value GetFpscrNZCV();
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void SetFpscrNZCV(const Value& new_fpscr_nzcv);
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Value Pack2x32To1x64(const Value& lo, const Value& hi);
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Value LeastSignificantWord(const Value& value);
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ResultAndCarry MostSignificantWord(const Value& value);
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Value LeastSignificantHalf(const Value& value);
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Value LeastSignificantByte(const Value& value);
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Value MostSignificantBit(const Value& value);
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Value IsZero(const Value& value);
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Value IsZero64(const Value& value);
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ResultAndCarry LogicalShiftLeft(const Value& value_in, const Value& shift_amount, const Value& carry_in);
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ResultAndCarry LogicalShiftRight(const Value& value_in, const Value& shift_amount, const Value& carry_in);
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Value LogicalShiftRight64(const Value& value_in, const Value& shift_amount);
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ResultAndCarry ArithmeticShiftRight(const Value& value_in, const Value& shift_amount, const Value& carry_in);
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ResultAndCarry RotateRight(const Value& value_in, const Value& shift_amount, const Value& carry_in);
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ResultAndCarry RotateRightExtended(const Value& value_in, const Value& carry_in);
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ResultAndCarryAndOverflow AddWithCarry(const Value& a, const Value& b, const Value& carry_in);
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Value Add(const Value& a, const Value& b);
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Value Add64(const Value& a, const Value& b);
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ResultAndCarryAndOverflow SubWithCarry(const Value& a, const Value& b, const Value& carry_in);
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Value Sub(const Value& a, const Value& b);
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Value Sub64(const Value& a, const Value& b);
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Value Mul(const Value& a, const Value& b);
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Value Mul64(const Value& a, const Value& b);
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Value And(const Value& a, const Value& b);
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Value Eor(const Value& a, const Value& b);
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Value Or(const Value& a, const Value& b);
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Value Not(const Value& a);
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Value SignExtendWordToLong(const Value& a);
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Value SignExtendHalfToWord(const Value& a);
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Value SignExtendByteToWord(const Value& a);
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Value ZeroExtendWordToLong(const Value& a);
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Value ZeroExtendHalfToWord(const Value& a);
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Value ZeroExtendByteToWord(const Value& a);
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Value ByteReverseWord(const Value& a);
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Value ByteReverseHalf(const Value& a);
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Value ByteReverseDual(const Value& a);
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Value PackedSaturatedAddU8(const Value& a, const Value& b);
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Value PackedSaturatedAddS8(const Value& a, const Value& b);
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Value PackedSaturatedSubU8(const Value& a, const Value& b);
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Value PackedSaturatedSubS8(const Value& a, const Value& b);
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Value PackedSaturatedAddU16(const Value& a, const Value& b);
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Value PackedSaturatedAddS16(const Value& a, const Value& b);
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Value PackedSaturatedSubU16(const Value& a, const Value& b);
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Value PackedSaturatedSubS16(const Value& a, const Value& b);
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Value TransferToFP32(const Value& a);
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Value TransferToFP64(const Value& a);
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Value TransferFromFP32(const Value& a);
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Value TransferFromFP64(const Value& a);
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Value FPAbs32(const Value& a);
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Value FPAbs64(const Value& a);
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Value FPAdd32(const Value& a, const Value& b, bool fpscr_controlled);
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Value FPAdd64(const Value& a, const Value& b, bool fpscr_controlled);
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Value FPDiv32(const Value& a, const Value& b, bool fpscr_controlled);
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Value FPDiv64(const Value& a, const Value& b, bool fpscr_controlled);
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Value FPMul32(const Value& a, const Value& b, bool fpscr_controlled);
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Value FPMul64(const Value& a, const Value& b, bool fpscr_controlled);
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Value FPNeg32(const Value& a);
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Value FPNeg64(const Value& a);
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Value FPSqrt32(const Value& a);
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Value FPSqrt64(const Value& a);
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Value FPSub32(const Value& a, const Value& b, bool fpscr_controlled);
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Value FPSub64(const Value& a, const Value& b, bool fpscr_controlled);
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Value FPDoubleToSingle(const Value& a, bool fpscr_controlled);
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Value FPSingleToDouble(const Value& a, bool fpscr_controlled);
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Value FPSingleToS32(const Value& a, bool round_towards_zero, bool fpscr_controlled);
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Value FPSingleToU32(const Value& a, bool round_towards_zero, bool fpscr_controlled);
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Value FPDoubleToS32(const Value& a, bool round_towards_zero, bool fpscr_controlled);
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Value FPDoubleToU32(const Value& a, bool round_towards_zero, bool fpscr_controlled);
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Value FPS32ToSingle(const Value& a, bool round_to_nearest, bool fpscr_controlled);
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Value FPU32ToSingle(const Value& a, bool round_to_nearest, bool fpscr_controlled);
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Value FPS32ToDouble(const Value& a, bool round_to_nearest, bool fpscr_controlled);
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Value FPU32ToDouble(const Value& a, bool round_to_nearest, bool fpscr_controlled);
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void ClearExclusive();
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void SetExclusive(const Value& vaddr, size_t byte_size);
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Value ReadMemory8(const Value& vaddr);
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Value ReadMemory16(const Value& vaddr);
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Value ReadMemory32(const Value& vaddr);
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Value ReadMemory64(const Value& vaddr);
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void WriteMemory8(const Value& vaddr, const Value& value);
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void WriteMemory16(const Value& vaddr, const Value& value);
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void WriteMemory32(const Value& vaddr, const Value& value);
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void WriteMemory64(const Value& vaddr, const Value& value);
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Value ExclusiveWriteMemory8(const Value& vaddr, const Value& value);
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Value ExclusiveWriteMemory16(const Value& vaddr, const Value& value);
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Value ExclusiveWriteMemory32(const Value& vaddr, const Value& value);
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Value ExclusiveWriteMemory64(const Value& vaddr, const Value& value_lo, const Value& value_hi);
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void Breakpoint();
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void SetTerm(const Terminal& terminal);
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private:
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Value Inst(Opcode op, std::initializer_list<Value> args);
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};
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} // namespace IR
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} // namespace Dynarmic
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