suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

Optimize

Browse source
This commit is contained in:
Liam 2022-11-13 20:11:08 -05:00
parent 48b0f6369b
commit ef2851d595
2 changed files with 8 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
src/dynarmic/backend/arm64/emit_arm64_a64.cpp
View file

@ -256,8 +256,8 @@ void EmitIR<IR::Opcode::A64SetW>(oaknut::CodeGenerator& code, EmitContext& ctx,
RegAlloc::Realize(Wvalue);
// TODO: Detect if Gpr vs Fpr is more appropriate
code.MOV(Wscratch0, Wvalue);
code.STR(Xscratch0, Xstate, offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg));
code.MOV(*Wvalue, Wvalue);
code.STR(Wvalue->toX(), Xstate, offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg));
}
template<>
@ -281,11 +281,7 @@ void EmitIR<IR::Opcode::A64SetS>(oaknut::CodeGenerator& code, EmitContext& ctx,
auto Svalue = ctx.reg_alloc.ReadS(args[1]);
RegAlloc::Realize(Svalue);
// TODO: Optimize
auto Qvalue = Svalue->toQ().B16();
code.FMOV(Wscratch0, Svalue);
code.EOR(Qvalue, Qvalue, Qvalue);
code.FMOV(Svalue, Wscratch0);
code.FMOV(Svalue, Svalue);
code.STR(Svalue->toQ(), Xstate, offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec));
}
@ -296,11 +292,7 @@ void EmitIR<IR::Opcode::A64SetD>(oaknut::CodeGenerator& code, EmitContext& ctx,
auto Dvalue = ctx.reg_alloc.ReadD(args[1]);
RegAlloc::Realize(Dvalue);
// TODO: Optimize
auto Qvalue = Dvalue->toQ().B16();
code.FMOV(Xscratch0, Dvalue);
code.EOR(Qvalue, Qvalue, Qvalue);
code.FMOV(Dvalue, Xscratch0);
code.FMOV(Dvalue, Dvalue);
code.STR(Dvalue->toQ(), Xstate, offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec));
}

8
src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
View file

@ -1431,8 +1431,8 @@ void EmitIR<IR::Opcode::ReplicateBit32>(oaknut::CodeGenerator& code, EmitContext
const u8 bit = args[1].GetImmediateU8();
RegAlloc::Realize(Wresult, Wvalue);
code.UBFX(Wscratch0, Wvalue, bit, 1);
code.SUB(Wresult, WZR, Wscratch0);
code.LSL(Wresult, Wvalue, 31 - bit);
code.ASR(Wresult, Wresult, 31);
}
template<>
@ -1445,8 +1445,8 @@ void EmitIR<IR::Opcode::ReplicateBit64>(oaknut::CodeGenerator& code, EmitContext
const u8 bit = args[1].GetImmediateU8();
RegAlloc::Realize(Xresult, Xvalue);
code.UBFX(Xscratch0, Xvalue, bit, 1);
code.SUB(Xresult, XZR, Xscratch0);
code.LSL(Xresult, Xvalue, 63 - bit);
code.ASR(Xresult, Xresult, 63);
}
static void EmitMaxMin32(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, oaknut::Cond cond) {