From ef2851d59547881e92db6eac338fb36661efea3f Mon Sep 17 00:00:00 2001
From: Liam <byteslice@airmail.cc>
Date: Sun, 13 Nov 2022 20:11:08 -0500
Subject: [PATCH] Optimize

---
 src/dynarmic/backend/arm64/emit_arm64_a64.cpp    | 16 ++++------------
 .../backend/arm64/emit_arm64_data_processing.cpp |  8 ++++----
 2 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/src/dynarmic/backend/arm64/emit_arm64_a64.cpp b/src/dynarmic/backend/arm64/emit_arm64_a64.cpp
index 71f72895..ca19890c 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_a64.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_a64.cpp
@@ -256,8 +256,8 @@ void EmitIR<IR::Opcode::A64SetW>(oaknut::CodeGenerator& code, EmitContext& ctx,
     RegAlloc::Realize(Wvalue);
 
     // TODO: Detect if Gpr vs Fpr is more appropriate
-    code.MOV(Wscratch0, Wvalue);
-    code.STR(Xscratch0, Xstate, offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg));
+    code.MOV(*Wvalue, Wvalue);
+    code.STR(Wvalue->toX(), Xstate, offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg));
 }
 
 template<>
@@ -281,11 +281,7 @@ void EmitIR<IR::Opcode::A64SetS>(oaknut::CodeGenerator& code, EmitContext& ctx,
     auto Svalue = ctx.reg_alloc.ReadS(args[1]);
     RegAlloc::Realize(Svalue);
 
-    // TODO: Optimize
-    auto Qvalue = Svalue->toQ().B16();
-    code.FMOV(Wscratch0, Svalue);
-    code.EOR(Qvalue, Qvalue, Qvalue);
-    code.FMOV(Svalue, Wscratch0);
+    code.FMOV(Svalue, Svalue);
     code.STR(Svalue->toQ(), Xstate, offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec));
 }
 
@@ -296,11 +292,7 @@ void EmitIR<IR::Opcode::A64SetD>(oaknut::CodeGenerator& code, EmitContext& ctx,
     auto Dvalue = ctx.reg_alloc.ReadD(args[1]);
     RegAlloc::Realize(Dvalue);
 
-    // TODO: Optimize
-    auto Qvalue = Dvalue->toQ().B16();
-    code.FMOV(Xscratch0, Dvalue);
-    code.EOR(Qvalue, Qvalue, Qvalue);
-    code.FMOV(Dvalue, Xscratch0);
+    code.FMOV(Dvalue, Dvalue);
     code.STR(Dvalue->toQ(), Xstate, offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec));
 }
 
diff --git a/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp b/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
index 23a6efa5..9321f45c 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
@@ -1431,8 +1431,8 @@ void EmitIR<IR::Opcode::ReplicateBit32>(oaknut::CodeGenerator& code, EmitContext
     const u8 bit = args[1].GetImmediateU8();
     RegAlloc::Realize(Wresult, Wvalue);
 
-    code.UBFX(Wscratch0, Wvalue, bit, 1);
-    code.SUB(Wresult, WZR, Wscratch0);
+    code.LSL(Wresult, Wvalue, 31 - bit);
+    code.ASR(Wresult, Wresult, 31);
 }
 
 template<>
@@ -1445,8 +1445,8 @@ void EmitIR<IR::Opcode::ReplicateBit64>(oaknut::CodeGenerator& code, EmitContext
     const u8 bit = args[1].GetImmediateU8();
     RegAlloc::Realize(Xresult, Xvalue);
 
-    code.UBFX(Xscratch0, Xvalue, bit, 1);
-    code.SUB(Xresult, XZR, Xscratch0);
+    code.LSL(Xresult, Xvalue, 63 - bit);
+    code.ASR(Xresult, Xresult, 63);
 }
 
 static void EmitMaxMin32(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, oaknut::Cond cond) {