suyu/dynarmic
28
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement SSHL (scalar)

Browse source
This commit is contained in:
Lioncash 2018-04-30 10:28:52 -04:00 committed by MerryMage
parent ef1e69a1e3
commit e71612d394
2 changed files with 14 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View file

@ -447,7 +447,7 @@ INST(ADDP_pair, "ADDP (scalar)", "01011
//INST(SQSUB_1, "SQSUB", "01011110zz1mmmmm001011nnnnnddddd")
INST(CMGT_reg_1, "CMGT (register)", "01011110zz1mmmmm001101nnnnnddddd")
INST(CMGE_reg_1, "CMGE (register)", "01011110zz1mmmmm001111nnnnnddddd")
//INST(SSHL_1, "SSHL", "01011110zz1mmmmm010001nnnnnddddd")
INST(SSHL_1, "SSHL", "01011110zz1mmmmm010001nnnnnddddd")
//INST(SQSHL_reg_1, "SQSHL (register)", "01011110zz1mmmmm010011nnnnnddddd")
//INST(SRSHL_1, "SRSHL", "01011110zz1mmmmm010101nnnnnddddd")
//INST(SQRSHL_1, "SQRSHL", "01011110zz1mmmmm010111nnnnnddddd")

13
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -130,6 +130,19 @@ bool TranslatorVisitor::CMTST_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SSHL_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size != 0b11) {
return ReservedValue();
}
const IR::U128 operand1 = V(64, Vn);
const IR::U128 operand2 = V(64, Vm);
const IR::U128 result = ir.VectorLogicalVShiftSigned(64, operand1, operand2);
V(64, Vd, result);
return true;
}
bool TranslatorVisitor::SUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size != 0b11) {
return ReservedValue();