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IR: Add ConditionalSelectNZCV instruction

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This commit is contained in:
MerryMage 2018-02-04 23:07:51 +00:00
parent 12c6f841c2
commit dd2a6684fe
4 changed files with 10 additions and 0 deletions
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4
src/backend_x64/emit_x64_data_processing.cpp
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@ -176,6 +176,10 @@ void EmitX64::EmitConditionalSelect64(EmitContext& ctx, IR::Inst* inst) {
EmitConditionalSelect(code, ctx, inst, 64);
}
void EmitX64::EmitConditionalSelectNZCV(EmitContext& ctx, IR::Inst* inst) {
EmitConditionalSelect(code, ctx, inst, 32);
}
static void EmitExtractRegister(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, int bit_size) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);

4
src/frontend/ir/ir_emitter.cpp
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@ -98,6 +98,10 @@ U64 IREmitter::ConditionalSelect(Cond cond, const U64& a, const U64& b) {
return Inst<U64>(Opcode::ConditionalSelect64, Value{cond}, a, b);
}
NZCV IREmitter::ConditionalSelect(Cond cond, const NZCV& a, const NZCV& b) {
return Inst<NZCV>(Opcode::ConditionalSelectNZCV, Value{cond}, a, b);
}
U32U64 IREmitter::ConditionalSelect(Cond cond, const U32U64& a, const U32U64& b) {
ASSERT(a.GetType() == b.GetType());
if (a.GetType() == Type::U32) {

1
src/frontend/ir/ir_emitter.h
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@ -79,6 +79,7 @@ public:
U1 TestBit(const U32U64& value, const U8& bit);
U32 ConditionalSelect(Cond cond, const U32& a, const U32& b);
U64 ConditionalSelect(Cond cond, const U64& a, const U64& b);
NZCV ConditionalSelect(Cond cond, const NZCV& a, const NZCV& b);
U32U64 ConditionalSelect(Cond cond, const U32U64& a, const U32U64& b);
NZCV NZCVFromPackedFlags(const U32& a);

1
src/frontend/ir/opcodes.inc
View file

@ -82,6 +82,7 @@ OPCODE(IsZero64, T::U1, T::U64
OPCODE(TestBit, T::U1, T::U64, T::U8 )
OPCODE(ConditionalSelect32, T::U32, T::Cond, T::U32, T::U32 )
OPCODE(ConditionalSelect64, T::U64, T::Cond, T::U64, T::U64 )
OPCODE(ConditionalSelectNZCV, T::NZCVFlags, T::Cond, T::NZCVFlags, T::NZCVFlags )
OPCODE(LogicalShiftLeft32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(LogicalShiftLeft64, T::U64, T::U64, T::U8 )
OPCODE(LogicalShiftRight32, T::U32, T::U32, T::U8, T::U1 )