From dd2a6684febb5bd747ff7f7fb5d25d280a57fda6 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 4 Feb 2018 23:07:51 +0000 Subject: [PATCH] IR: Add ConditionalSelectNZCV instruction --- src/backend_x64/emit_x64_data_processing.cpp | 4 ++++ src/frontend/ir/ir_emitter.cpp | 4 ++++ src/frontend/ir/ir_emitter.h | 1 + src/frontend/ir/opcodes.inc | 1 + 4 files changed, 10 insertions(+) diff --git a/src/backend_x64/emit_x64_data_processing.cpp b/src/backend_x64/emit_x64_data_processing.cpp index bf595811..2c187f68 100644 --- a/src/backend_x64/emit_x64_data_processing.cpp +++ b/src/backend_x64/emit_x64_data_processing.cpp @@ -176,6 +176,10 @@ void EmitX64::EmitConditionalSelect64(EmitContext& ctx, IR::Inst* inst) { EmitConditionalSelect(code, ctx, inst, 64); } +void EmitX64::EmitConditionalSelectNZCV(EmitContext& ctx, IR::Inst* inst) { + EmitConditionalSelect(code, ctx, inst, 32); +} + static void EmitExtractRegister(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, int bit_size) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index eb367382..22a81ee1 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -98,6 +98,10 @@ U64 IREmitter::ConditionalSelect(Cond cond, const U64& a, const U64& b) { return Inst(Opcode::ConditionalSelect64, Value{cond}, a, b); } +NZCV IREmitter::ConditionalSelect(Cond cond, const NZCV& a, const NZCV& b) { + return Inst(Opcode::ConditionalSelectNZCV, Value{cond}, a, b); +} + U32U64 IREmitter::ConditionalSelect(Cond cond, const U32U64& a, const U32U64& b) { ASSERT(a.GetType() == b.GetType()); if (a.GetType() == Type::U32) { diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 932cc78d..d35903f8 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -79,6 +79,7 @@ public: U1 TestBit(const U32U64& value, const U8& bit); U32 ConditionalSelect(Cond cond, const U32& a, const U32& b); U64 ConditionalSelect(Cond cond, const U64& a, const U64& b); + NZCV ConditionalSelect(Cond cond, const NZCV& a, const NZCV& b); U32U64 ConditionalSelect(Cond cond, const U32U64& a, const U32U64& b); NZCV NZCVFromPackedFlags(const U32& a); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index 0b8d04f6..c397d411 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -82,6 +82,7 @@ OPCODE(IsZero64, T::U1, T::U64 OPCODE(TestBit, T::U1, T::U64, T::U8 ) OPCODE(ConditionalSelect32, T::U32, T::Cond, T::U32, T::U32 ) OPCODE(ConditionalSelect64, T::U64, T::Cond, T::U64, T::U64 ) +OPCODE(ConditionalSelectNZCV, T::NZCVFlags, T::Cond, T::NZCVFlags, T::NZCVFlags ) OPCODE(LogicalShiftLeft32, T::U32, T::U32, T::U8, T::U1 ) OPCODE(LogicalShiftLeft64, T::U64, T::U64, T::U8 ) OPCODE(LogicalShiftRight32, T::U32, T::U32, T::U8, T::U1 )