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A64: Implement SADDL/SADDL2

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Lioncash 2018-04-05 09:41:59 -04:00 committed by MerryMage
parent 5c9e7f328d
commit d456fb85c8
2 changed files with 17 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -675,7 +675,7 @@ INST(RBIT_asimd, "RBIT (vector)", "0Q101
//INST(UMINV, "UMINV", "0Q101110zz110001101010nnnnnddddd")
// Data Processing - FP and SIMD - SIMD three different
//INST(SADDL, "SADDL, SADDL2", "0Q001110zz1mmmmm000000nnnnnddddd")
INST(SADDL, "SADDL, SADDL2", "0Q001110zz1mmmmm000000nnnnnddddd")
INST(SADDW, "SADDW, SADDW2", "0Q001110zz1mmmmm000100nnnnnddddd")
//INST(SSUBL, "SSUBL, SSUBL2", "0Q001110zz1mmmmm001000nnnnnddddd")
INST(SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd")

16
src/frontend/A64/translate/impl/simd_three_different.cpp
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@ -8,6 +8,22 @@
namespace Dynarmic::A64 {
bool TranslatorVisitor::SADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t part = Q ? 1 : 0;
const IR::U128 operand1 = ir.VectorSignExtend(esize, Vpart(64, Vn, part));
const IR::U128 operand2 = ir.VectorSignExtend(esize, Vpart(64, Vm, part));
const IR::U128 result = ir.VectorAdd(esize * 2, operand1, operand2);
V(128, Vd, result);
return true;
}
bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();