From d456fb85c8ca223be10ff433f6c429187f1c7080 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Thu, 5 Apr 2018 09:41:59 -0400
Subject: [PATCH] A64: Implement SADDL/SADDL2

---
 src/frontend/A64/decoder/a64.inc                 |  2 +-
 .../A64/translate/impl/simd_three_different.cpp  | 16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index d53faec0..368fadcb 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -675,7 +675,7 @@ INST(RBIT_asimd,             "RBIT (vector)",                             "0Q101
 //INST(UMINV,                  "UMINV",                                     "0Q101110zz110001101010nnnnnddddd")
 
 // Data Processing - FP and SIMD - SIMD three different
-//INST(SADDL,                  "SADDL, SADDL2",                             "0Q001110zz1mmmmm000000nnnnnddddd")
+INST(SADDL,                  "SADDL, SADDL2",                             "0Q001110zz1mmmmm000000nnnnnddddd")
 INST(SADDW,                  "SADDW, SADDW2",                             "0Q001110zz1mmmmm000100nnnnnddddd")
 //INST(SSUBL,                  "SSUBL, SSUBL2",                             "0Q001110zz1mmmmm001000nnnnnddddd")
 INST(SSUBW,                  "SSUBW, SSUBW2",                             "0Q001110zz1mmmmm001100nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_three_different.cpp b/src/frontend/A64/translate/impl/simd_three_different.cpp
index 9a6f013b..606a8c36 100644
--- a/src/frontend/A64/translate/impl/simd_three_different.cpp
+++ b/src/frontend/A64/translate/impl/simd_three_different.cpp
@@ -8,6 +8,22 @@
 
 namespace Dynarmic::A64 {
 
+bool TranslatorVisitor::SADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
+    if (size == 0b11) {
+        return ReservedValue();
+    }
+
+    const size_t esize = 8 << size.ZeroExtend();
+    const size_t part = Q ? 1 : 0;
+
+    const IR::U128 operand1 = ir.VectorSignExtend(esize, Vpart(64, Vn, part));
+    const IR::U128 operand2 = ir.VectorSignExtend(esize, Vpart(64, Vm, part));
+    const IR::U128 result = ir.VectorAdd(esize * 2, operand1, operand2);
+
+    V(128, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
     if (size == 0b11) {
         return ReservedValue();