A64: Implement SADDL/SADDL2
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2 changed files with 17 additions and 1 deletions
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@ -675,7 +675,7 @@ INST(RBIT_asimd, "RBIT (vector)", "0Q101
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//INST(UMINV, "UMINV", "0Q101110zz110001101010nnnnnddddd")
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//INST(UMINV, "UMINV", "0Q101110zz110001101010nnnnnddddd")
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// Data Processing - FP and SIMD - SIMD three different
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// Data Processing - FP and SIMD - SIMD three different
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//INST(SADDL, "SADDL, SADDL2", "0Q001110zz1mmmmm000000nnnnnddddd")
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INST(SADDL, "SADDL, SADDL2", "0Q001110zz1mmmmm000000nnnnnddddd")
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INST(SADDW, "SADDW, SADDW2", "0Q001110zz1mmmmm000100nnnnnddddd")
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INST(SADDW, "SADDW, SADDW2", "0Q001110zz1mmmmm000100nnnnnddddd")
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//INST(SSUBL, "SSUBL, SSUBL2", "0Q001110zz1mmmmm001000nnnnnddddd")
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//INST(SSUBL, "SSUBL, SSUBL2", "0Q001110zz1mmmmm001000nnnnnddddd")
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INST(SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd")
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INST(SSUBW, "SSUBW, SSUBW2", "0Q001110zz1mmmmm001100nnnnnddddd")
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@ -8,6 +8,22 @@
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namespace Dynarmic::A64 {
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namespace Dynarmic::A64 {
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bool TranslatorVisitor::SADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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const size_t esize = 8 << size.ZeroExtend();
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const size_t part = Q ? 1 : 0;
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const IR::U128 operand1 = ir.VectorSignExtend(esize, Vpart(64, Vn, part));
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const IR::U128 operand2 = ir.VectorSignExtend(esize, Vpart(64, Vm, part));
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const IR::U128 result = ir.VectorAdd(esize * 2, operand1, operand2);
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V(128, Vd, result);
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return true;
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}
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bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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bool TranslatorVisitor::SADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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if (size == 0b11) {
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return ReservedValue();
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return ReservedValue();
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