VFP: Implement VNEG
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4 changed files with 23 additions and 1 deletions
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@ -78,7 +78,7 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
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// VMOV_imm
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// VMOV_reg
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INST(&V::vfp2_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm"),
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// VNEG
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INST(&V::vfp2_VNEG, "VNEG", "cccc11101D110001dddd101z01M0mmmm"),
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// VSQRT
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// VCMP
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// VCMPE
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@ -599,6 +599,10 @@ public:
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std::string vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
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return Common::StringFromFormat("vadd%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
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}
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std::string vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
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return Common::StringFromFormat("vneg%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
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}
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};
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std::string DisassembleArm(u32 instruction) {
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@ -331,6 +331,7 @@ struct ArmTranslatorVisitor final {
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// Floating-point misc instructions
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bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
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bool vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
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};
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} // namespace Arm
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@ -209,5 +209,22 @@ bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool
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return true;
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}
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bool ArmTranslatorVisitor::vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
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if (ir.current_location.FPSCR_Len() != 1 || ir.current_location.FPSCR_Stride() != 1)
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return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
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ExtReg d = ToExtReg(sz, Vd, D);
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ExtReg m = ToExtReg(sz, Vm, M);
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// VNEG.{F32,F64} <{S,D}d>, <{S,D}m>
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if (ConditionPassed(cond)) {
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auto a = ir.GetExtendedRegister(m);
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auto result = sz
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? ir.FPNeg64(a)
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: ir.FPNeg32(a);
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ir.SetExtendedRegister(d, result);
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}
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return true;
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}
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} // namespace Arm
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} // namespace Dynarmic
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