From cd8e7c050447f8ea0e717dfca2c7940a99157ded Mon Sep 17 00:00:00 2001
From: MerryMage <MerryMage@users.noreply.github.com>
Date: Sun, 7 Aug 2016 12:04:21 +0100
Subject: [PATCH] VFP: Implement VNEG

---
 src/frontend/decoder/vfp2.h                     |  2 +-
 src/frontend/disassembler/disassembler_arm.cpp  |  4 ++++
 .../translate/translate_arm/translate_arm.h     |  1 +
 src/frontend/translate/translate_arm/vfp2.cpp   | 17 +++++++++++++++++
 4 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/src/frontend/decoder/vfp2.h b/src/frontend/decoder/vfp2.h
index ec2e8e80..0feb013c 100644
--- a/src/frontend/decoder/vfp2.h
+++ b/src/frontend/decoder/vfp2.h
@@ -78,7 +78,7 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
     // VMOV_imm
     // VMOV_reg
     INST(&V::vfp2_VABS,       "VABS",                "cccc11101D110000dddd101z11M0mmmm"),
-    // VNEG
+    INST(&V::vfp2_VNEG,       "VNEG",                "cccc11101D110001dddd101z01M0mmmm"),
     // VSQRT
     // VCMP
     // VCMPE
diff --git a/src/frontend/disassembler/disassembler_arm.cpp b/src/frontend/disassembler/disassembler_arm.cpp
index a09ecc83..66bf19ea 100644
--- a/src/frontend/disassembler/disassembler_arm.cpp
+++ b/src/frontend/disassembler/disassembler_arm.cpp
@@ -599,6 +599,10 @@ public:
     std::string vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
         return Common::StringFromFormat("vadd%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
     }
+
+    std::string vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
+        return Common::StringFromFormat("vneg%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
+    }
 };
 
 std::string DisassembleArm(u32 instruction) {
diff --git a/src/frontend/translate/translate_arm/translate_arm.h b/src/frontend/translate/translate_arm/translate_arm.h
index 9cf68973..5555e7c5 100644
--- a/src/frontend/translate/translate_arm/translate_arm.h
+++ b/src/frontend/translate/translate_arm/translate_arm.h
@@ -331,6 +331,7 @@ struct ArmTranslatorVisitor final {
 
     // Floating-point misc instructions
     bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
+    bool vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
 };
 
 } // namespace Arm
diff --git a/src/frontend/translate/translate_arm/vfp2.cpp b/src/frontend/translate/translate_arm/vfp2.cpp
index d9a1c0e6..52877abe 100644
--- a/src/frontend/translate/translate_arm/vfp2.cpp
+++ b/src/frontend/translate/translate_arm/vfp2.cpp
@@ -209,5 +209,22 @@ bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool
     return true;
 }
 
+bool ArmTranslatorVisitor::vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
+    if (ir.current_location.FPSCR_Len() != 1 || ir.current_location.FPSCR_Stride() != 1)
+        return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
+
+    ExtReg d = ToExtReg(sz, Vd, D);
+    ExtReg m = ToExtReg(sz, Vm, M);
+    // VNEG.{F32,F64} <{S,D}d>, <{S,D}m>
+    if (ConditionPassed(cond)) {
+        auto a = ir.GetExtendedRegister(m);
+        auto result = sz
+                      ? ir.FPNeg64(a)
+                      : ir.FPNeg32(a);
+        ir.SetExtendedRegister(d, result);
+    }
+    return true;
+}
+
 } // namespace Arm
 } // namespace Dynarmic