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VFP: Implement VNEG

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This commit is contained in:
MerryMage 2016-08-07 12:04:21 +01:00
parent da33af5abe
commit cd8e7c0504
4 changed files with 23 additions and 1 deletions
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2
src/frontend/decoder/vfp2.h
View file

@ -78,7 +78,7 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
// VMOV_imm // VMOV_imm
// VMOV_reg // VMOV_reg
INST(&V::vfp2_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm"), INST(&V::vfp2_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm"),
// VNEG INST(&V::vfp2_VNEG, "VNEG", "cccc11101D110001dddd101z01M0mmmm"),
// VSQRT // VSQRT
// VCMP // VCMP
// VCMPE // VCMPE

4
src/frontend/disassembler/disassembler_arm.cpp
View file

@ -599,6 +599,10 @@ public:
std::string vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) { std::string vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
return Common::StringFromFormat("vadd%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); return Common::StringFromFormat("vadd%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
} }
std::string vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
return Common::StringFromFormat("vneg%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
}
}; };
std::string DisassembleArm(u32 instruction) { std::string DisassembleArm(u32 instruction) {

1
src/frontend/translate/translate_arm/translate_arm.h
View file

@ -331,6 +331,7 @@ struct ArmTranslatorVisitor final {
// Floating-point misc instructions // Floating-point misc instructions
bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
}; };
} // namespace Arm } // namespace Arm

17
src/frontend/translate/translate_arm/vfp2.cpp
View file

@ -209,5 +209,22 @@ bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool
return true; return true;
} }
bool ArmTranslatorVisitor::vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
if (ir.current_location.FPSCR_Len() != 1 || ir.current_location.FPSCR_Stride() != 1)
return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
ExtReg d = ToExtReg(sz, Vd, D);
ExtReg m = ToExtReg(sz, Vm, M);
// VNEG.{F32,F64} <{S,D}d>, <{S,D}m>
if (ConditionPassed(cond)) {
auto a = ir.GetExtendedRegister(m);
auto result = sz
? ir.FPNeg64(a)
: ir.FPNeg32(a);
ir.SetExtendedRegister(d, result);
}
return true;
}
} // namespace Arm } // namespace Arm
} // namespace Dynarmic } // namespace Dynarmic