suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

simd: Relocate REV16, REV32 and REV64 vector variants to the proper file

Browse source 
These aren't scalar instruction variants.
This commit is contained in:
Lioncash 2018-04-15 07:18:11 -04:00 committed by MerryMage
parent 19e276d10f
commit b4f3051e4b
2 changed files with 81 additions and 81 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

81
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
View file

@ -8,87 +8,6 @@
namespace Dynarmic::A64 { namespace Dynarmic::A64 {
bool TranslatorVisitor::REV16_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size != 0) {
return UnallocatedEncoding();
}
const size_t datasize = Q ? 128 : 64;
constexpr size_t esize = 16;
const IR::U128 data = V(datasize, Vn);
const IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, 8),
ir.VectorLogicalShiftLeft(esize, data, 8));
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::REV32_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
const u32 zext_size = size.ZeroExtend();
if (zext_size > 1) {
return UnallocatedEncoding();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = 16 << zext_size;
const u8 shift = static_cast<u8>(8 << zext_size);
const IR::U128 data = V(datasize, Vn);
// TODO: Consider factoring byte swapping code out into its own opcode.
// Technically the rest of the following code can be a PSHUFB
// in the presence of SSSE3.
IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, shift),
ir.VectorLogicalShiftLeft(esize, data, shift));
// If dealing with 8-bit elements we'll need to shuffle the bytes in each halfword
// e.g. Assume the following numbers point out bytes in a 32-bit word, we're essentially
// changing [3, 2, 1, 0] to [2, 3, 0, 1]
if (zext_size == 0) {
result = ir.VectorShuffleLowHalfwords(result, 0b10110001);
result = ir.VectorShuffleHighHalfwords(result, 0b10110001);
}
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::REV64_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
const u32 zext_size = size.ZeroExtend();
if (zext_size >= 3) {
return UnallocatedEncoding();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = 16 << zext_size;
const u8 shift = static_cast<u8>(8 << zext_size);
const IR::U128 data = V(datasize, Vn);
// TODO: Consider factoring byte swapping code out into its own opcode.
// Technically the rest of the following code can be a PSHUFB
// in the presence of SSSE3.
IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, shift),
ir.VectorLogicalShiftLeft(esize, data, shift));
switch (zext_size) {
case 0: // 8-bit elements
result = ir.VectorShuffleLowHalfwords(result, 0b00011011);
result = ir.VectorShuffleHighHalfwords(result, 0b00011011);
break;
case 1: // 16-bit elements
result = ir.VectorShuffleLowHalfwords(result, 0b01001110);
result = ir.VectorShuffleHighHalfwords(result, 0b01001110);
break;
}
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) { bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
const auto esize = sz ? 64 : 32; const auto esize = sz ? 64 : 32;

81
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -135,4 +135,85 @@ bool TranslatorVisitor::RBIT_asimd(bool Q, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::REV16_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size != 0) {
return UnallocatedEncoding();
}
const size_t datasize = Q ? 128 : 64;
constexpr size_t esize = 16;
const IR::U128 data = V(datasize, Vn);
const IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, 8),
ir.VectorLogicalShiftLeft(esize, data, 8));
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::REV32_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
const u32 zext_size = size.ZeroExtend();
if (zext_size > 1) {
return UnallocatedEncoding();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = 16 << zext_size;
const u8 shift = static_cast<u8>(8 << zext_size);
const IR::U128 data = V(datasize, Vn);
// TODO: Consider factoring byte swapping code out into its own opcode.
// Technically the rest of the following code can be a PSHUFB
// in the presence of SSSE3.
IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, shift),
ir.VectorLogicalShiftLeft(esize, data, shift));
// If dealing with 8-bit elements we'll need to shuffle the bytes in each halfword
// e.g. Assume the following numbers point out bytes in a 32-bit word, we're essentially
// changing [3, 2, 1, 0] to [2, 3, 0, 1]
if (zext_size == 0) {
result = ir.VectorShuffleLowHalfwords(result, 0b10110001);
result = ir.VectorShuffleHighHalfwords(result, 0b10110001);
}
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::REV64_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
const u32 zext_size = size.ZeroExtend();
if (zext_size >= 3) {
return UnallocatedEncoding();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = 16 << zext_size;
const u8 shift = static_cast<u8>(8 << zext_size);
const IR::U128 data = V(datasize, Vn);
// TODO: Consider factoring byte swapping code out into its own opcode.
// Technically the rest of the following code can be a PSHUFB
// in the presence of SSSE3.
IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, shift),
ir.VectorLogicalShiftLeft(esize, data, shift));
switch (zext_size) {
case 0: // 8-bit elements
result = ir.VectorShuffleLowHalfwords(result, 0b00011011);
result = ir.VectorShuffleHighHalfwords(result, 0b00011011);
break;
case 1: // 16-bit elements
result = ir.VectorShuffleLowHalfwords(result, 0b01001110);
result = ir.VectorShuffleHighHalfwords(result, 0b01001110);
break;
}
V(datasize, Vd, result);
return true;
}
} // namespace Dynarmic::A64 } // namespace Dynarmic::A64