suyu/dynarmic
28
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement CMEQ (register, scalar)

Browse source
This commit is contained in:
Lioncash 2018-04-15 05:39:12 -04:00 committed by MerryMage
parent 5b8c9e5146
commit 19e276d10f
2 changed files with 8 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View file

@ -463,7 +463,7 @@ INST(CMHS_1, "CMHS (register)", "01111
//INST(URSHL_1, "URSHL", "01111110zz1mmmmm010101nnnnnddddd")
//INST(UQRSHL_1, "UQRSHL", "01111110zz1mmmmm010111nnnnnddddd")
INST(SUB_1, "SUB (vector)", "01111110zz1mmmmm100001nnnnnddddd")
//INST(CMEQ_reg_1, "CMEQ (register)", "01111110zz1mmmmm100011nnnnnddddd")
INST(CMEQ_reg_1, "CMEQ (register)", "01111110zz1mmmmm100011nnnnnddddd")
//INST(SQRDMULH_vec_1, "SQRDMULH (vector)", "01111110zz1mmmmm101101nnnnnddddd")
// Data Processing - FP and SIMD - SIMD Scalar shift by immediate

7
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -10,6 +10,7 @@
namespace Dynarmic::A64 {
namespace {
enum class ComparisonType {
EQ,
GE,
GT,
HI,
@ -29,6 +30,8 @@ bool ScalarCompare(TranslatorVisitor& v, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Co
const IR::U128 result = [&] {
switch (type) {
case ComparisonType::EQ:
return v.ir.VectorEqual(esize, operand1, operand2);
case ComparisonType::GE:
return v.ir.VectorGreaterEqualSigned(esize, operand1, operand2);
case ComparisonType::GT:
@ -60,6 +63,10 @@ bool TranslatorVisitor::ADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::CMEQ_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return ScalarCompare(*this, size, Vm, Vn, Vd, ComparisonType::EQ);
}
bool TranslatorVisitor::CMGE_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return ScalarCompare(*this, size, Vm, Vn, Vd, ComparisonType::GE);
}