TranslateArm: VSTR: Correct behaviour in big-endian mode
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2 changed files with 11 additions and 7 deletions
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@ -388,8 +388,11 @@ bool ArmTranslatorVisitor::vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd
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auto address = U ? ir.Add(base, ir.Imm32(imm32)) : ir.Sub(base, ir.Imm32(imm32));
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auto address = U ? ir.Add(base, ir.Imm32(imm32)) : ir.Sub(base, ir.Imm32(imm32));
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if (sz) {
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if (sz) {
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auto d_u64 = ir.TransferFromFP64(ir.GetExtendedRegister(d));
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auto d_u64 = ir.TransferFromFP64(ir.GetExtendedRegister(d));
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ir.WriteMemory32(address, ir.LeastSignificantWord(d_u64));
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auto lo = ir.LeastSignificantWord(d_u64);
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ir.WriteMemory32(ir.Add(address, ir.Imm32(4)), ir.MostSignificantWord(d_u64).result);
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auto hi = ir.MostSignificantWord(d_u64).result;
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if (ir.current_location.EFlag()) std::swap(lo, hi);
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ir.WriteMemory32(address, lo);
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ir.WriteMemory32(ir.Add(address, ir.Imm32(4)), hi);
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} else {
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} else {
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ir.WriteMemory32(address, ir.TransferFromFP32(ir.GetExtendedRegister(d)));
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ir.WriteMemory32(address, ir.TransferFromFP32(ir.GetExtendedRegister(d)));
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}
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}
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@ -424,13 +424,14 @@ TEST_CASE("VFP: VMOV", "[JitX64][vfp]") {
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TEST_CASE("VFP: VMOV (reg), VLDR, VSTR", "[JitX64][vfp]") {
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TEST_CASE("VFP: VMOV (reg), VLDR, VSTR", "[JitX64][vfp]") {
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const std::array<InstructionGenerator, 3> instructions = {{
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const std::array<InstructionGenerator, 4> instructions = {{
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InstructionGenerator("cccc11101D110000dddd101z01M0mmmm"),
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InstructionGenerator("1111000100000001000000e000000000"), // SETEND
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InstructionGenerator("cccc1101UD01nnnndddd101zvvvvvvvv"),
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InstructionGenerator("cccc11101D110000dddd101z01M0mmmm"), // VMOV (reg)
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InstructionGenerator("cccc1101UD00nnnndddd101zvvvvvvvv"),
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InstructionGenerator("cccc1101UD01nnnndddd101zvvvvvvvv"), // VLDR
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InstructionGenerator("cccc1101UD00nnnndddd101zvvvvvvvv"), // VSTR
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}};
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}};
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FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 {
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FuzzJitArm(5, 6, 10000, [&instructions]() -> u32 {
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return instructions[RandInt<size_t>(0, instructions.size() - 1)].Generate();
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return instructions[RandInt<size_t>(0, instructions.size() - 1)].Generate();
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});
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});
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}
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}
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