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backend/arm64: Implement LeastSignificantHalf

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Merry 2022-07-22 23:59:31 +01:00 committed by merry
parent 163ed9b185
commit a33d186fea
1 changed files with 7 additions and 4 deletions
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11
src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
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@ -84,10 +84,13 @@ void EmitIR<IR::Opcode::LeastSignificantWord>(oaknut::CodeGenerator& code, EmitC
template<>
void EmitIR<IR::Opcode::LeastSignificantHalf>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code;
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
auto Wresult = ctx.reg_alloc.WriteW(inst);
auto Woperand = ctx.reg_alloc.ReadW(args[0]);
RegAlloc::Realize(Wresult, Woperand);
code.UXTH(Wresult, Woperand); // TODO: Zext elimination
}
template<>