From a07c05ea5146ce0eb9b35e785876b1f1ab93d3b3 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Fri, 2 Feb 2018 22:39:24 +0000 Subject: [PATCH] A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP) --- src/frontend/A64/decoder/a64.inc | 4 ++-- src/frontend/A64/translate/impl/impl.h | 4 ++-- .../impl/load_store_register_immediate.cpp | 20 +++++++++++++++++++ 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index c426481c..ad3a01a0 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -180,8 +180,8 @@ INST(STURx_LDURx, "STURx/LDURx", "zz111 INST(UnallocatedEncoding, "", "111110001-0---------00----------") INST(UnallocatedEncoding, "", "10111000110---------00----------") //INST(PRFM_imm, "PRFM (immediate)", "1111100110iiiiiiiiiiiinnnnnttttt") -//INST(STUR_fpsimd, "STUR (SIMD&FP)", "zz111100-00iiiiiiiii00nnnnnttttt") -//INST(LDUR_fpsimd, "LDUR (SIMD&FP)", "zz111100-10iiiiiiiii00nnnnnttttt") +INST(STUR_fpsimd, "STUR (SIMD&FP)", "zz111100o00iiiiiiiii00nnnnnttttt") +INST(LDUR_fpsimd, "LDUR (SIMD&FP)", "zz111100o10iiiiiiiii00nnnnnttttt") // Loads and stores - Load/Store register (immediate pre/post-indexed) INST(STRx_LDRx_imm_1, "STRx/LDRx (immediate)", "zz111000oo0iiiiiiiiip1nnnnnttttt") diff --git a/src/frontend/A64/translate/impl/impl.h b/src/frontend/A64/translate/impl/impl.h index 0dfec6d1..c2d81c7a 100644 --- a/src/frontend/A64/translate/impl/impl.h +++ b/src/frontend/A64/translate/impl/impl.h @@ -246,8 +246,8 @@ struct TranslatorVisitor final { bool STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt); bool LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn, Vec Vt); bool LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt); - bool STUR_fpsimd(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt); - bool LDUR_fpsimd(Imm<2> size, Imm<9> imm9, Reg Rn, Vec Vt); + bool STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt); + bool LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt); // Loads and stores - Load/Store register (unprivileged) bool STTRB(Imm<9> imm9, Reg Rn, Reg Rt); diff --git a/src/frontend/A64/translate/impl/load_store_register_immediate.cpp b/src/frontend/A64/translate/impl/load_store_register_immediate.cpp index 2d28550a..1c194ac7 100644 --- a/src/frontend/A64/translate/impl/load_store_register_immediate.cpp +++ b/src/frontend/A64/translate/impl/load_store_register_immediate.cpp @@ -193,4 +193,24 @@ bool TranslatorVisitor::LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm1 return LoadStoreSIMD(*this, ir, wback, postindex, scale, offset, MemOp::LOAD, Rn, Vt); } +bool TranslatorVisitor::STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) { + const bool wback = false; + const bool postindex = false; + const size_t scale = concatenate(opc_1, size).ZeroExtend(); + if (scale > 4) return UnallocatedEncoding(); + const u64 offset = imm9.SignExtend(); + + return LoadStoreSIMD(*this, ir, wback, postindex, scale, offset, MemOp::STORE, Rn, Vt); +} + +bool TranslatorVisitor::LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) { + const bool wback = false; + const bool postindex = false; + const size_t scale = concatenate(opc_1, size).ZeroExtend(); + if (scale > 4) return UnallocatedEncoding(); + const u64 offset = imm9.SignExtend(); + + return LoadStoreSIMD(*this, ir, wback, postindex, scale, offset, MemOp::LOAD, Rn, Vt); +} + } // namespace Dynarmic::A64