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A32: Implement ASIMD VRSQRTE

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This commit is contained in:
MerryMage 2020-06-20 15:13:18 +01:00
parent 8912496206
commit 92cb4a5a34
8 changed files with 38 additions and 11 deletions
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2
src/backend/x64/emit_x64_vector_floating_point.cpp
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@ -1304,7 +1304,7 @@ void EmitX64::EmitFPVectorRoundInt64(EmitContext& ctx, IR::Inst* inst) {
template<typename FPT> template<typename FPT>
static void EmitRSqrtEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { static void EmitRSqrtEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
EmitTwoOpFallback(code, ctx, inst, [](VectorArray<FPT>& result, const VectorArray<FPT>& operand, FP::FPCR fpcr, FP::FPSR& fpsr) { EmitTwoOpFallback<FpcrControlledArgument::Present>(code, ctx, inst, [](VectorArray<FPT>& result, const VectorArray<FPT>& operand, FP::FPCR fpcr, FP::FPSR& fpsr) {
for (size_t i = 0; i < result.size(); i++) { for (size_t i = 0; i < result.size(); i++) {
result[i] = FP::FPRSqrtEstimate<FPT>(operand[i], fpcr, fpsr); result[i] = FP::FPRSqrtEstimate<FPT>(operand[i], fpcr, fpsr);
} }

2
src/frontend/A32/decoder/asimd.inc
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@ -104,7 +104,7 @@ INST(asimd_VSWP, "VSWP", "111100111D110010dddd000
//INST(asimd_VSHLL_max, "VSHLL_max", "111100111-11--10----001100-0----") // ASIMD //INST(asimd_VSHLL_max, "VSHLL_max", "111100111-11--10----001100-0----") // ASIMD
//INST(asimd_VCVT_half, "VCVT (half-precision)", "111100111-11--10----011x00-0----") // ASIMD //INST(asimd_VCVT_half, "VCVT (half-precision)", "111100111-11--10----011x00-0----") // ASIMD
INST(asimd_VRECPE, "VRECPE", "111100111D11zz11dddd010F0QM0mmmm") // ASIMD INST(asimd_VRECPE, "VRECPE", "111100111D11zz11dddd010F0QM0mmmm") // ASIMD
//INST(asimd_VRSQRTE, "VRSQRTE", "111100111-11--11----010x1x-0----") // ASIMD INST(asimd_VRSQRTE, "VRSQRTE", "111100111D11zz11dddd010F1QM0mmmm") // ASIMD
//INST(asimd_VCVT_integer, "VCVT (integer)", "111100111-11--11----011xxx-0----") // ASIMD //INST(asimd_VCVT_integer, "VCVT (integer)", "111100111-11--11----011xxx-0----") // ASIMD
// One register and modified immediate // One register and modified immediate

26
src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
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@ -379,4 +379,30 @@ bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bo
return true; return true;
} }
bool ArmTranslatorVisitor::asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
if (sz == 0b00 || sz == 0b11) {
return UndefinedInstruction();
}
if (!F && sz == 0b01) {
// TODO: Implement 16-bit VectorUnsignedRecipEstimate
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto result = F ? ir.FPVectorRSqrtEstimate(esize, reg_m, false)
: ir.VectorUnsignedRecipSqrtEstimate(reg_m);
ir.SetVector(d, result);
return true;
}
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -500,6 +500,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
// Advanced SIMD load/store structures // Advanced SIMD load/store structures
bool v8_VST_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m); bool v8_VST_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m);

8
src/frontend/ir/ir_emitter.cpp
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@ -2479,14 +2479,14 @@ U128 IREmitter::FPVectorRoundInt(size_t esize, const U128& operand, FP::Rounding
UNREACHABLE(); UNREACHABLE();
} }
U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) { U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a, bool fpcr_controlled) {
switch (esize) { switch (esize) {
case 16: case 16:
return Inst<U128>(Opcode::FPVectorRSqrtEstimate16, a); return Inst<U128>(Opcode::FPVectorRSqrtEstimate16, a, Imm1(fpcr_controlled));
case 32: case 32:
return Inst<U128>(Opcode::FPVectorRSqrtEstimate32, a); return Inst<U128>(Opcode::FPVectorRSqrtEstimate32, a, Imm1(fpcr_controlled));
case 64: case 64:
return Inst<U128>(Opcode::FPVectorRSqrtEstimate64, a); return Inst<U128>(Opcode::FPVectorRSqrtEstimate64, a, Imm1(fpcr_controlled));
} }
UNREACHABLE(); UNREACHABLE();
} }

2
src/frontend/ir/ir_emitter.h
View file

@ -363,7 +363,7 @@ public:
U128 FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled = true); U128 FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled = true);
U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact); U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact);
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a); U128 FPVectorRSqrtEstimate(size_t esize, const U128& a, bool fpcr_controlled = true);
U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorSqrt(size_t esize, const U128& a); U128 FPVectorSqrt(size_t esize, const U128& a);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); U128 FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);

6
src/frontend/ir/opcodes.inc
View file

@ -622,9 +622,9 @@ OPCODE(FPVectorRecipStepFused64, U128, U128
OPCODE(FPVectorRoundInt16, U128, U128, U8, U1 ) OPCODE(FPVectorRoundInt16, U128, U128, U8, U1 )
OPCODE(FPVectorRoundInt32, U128, U128, U8, U1 ) OPCODE(FPVectorRoundInt32, U128, U128, U8, U1 )
OPCODE(FPVectorRoundInt64, U128, U128, U8, U1 ) OPCODE(FPVectorRoundInt64, U128, U128, U8, U1 )
OPCODE(FPVectorRSqrtEstimate16, U128, U128 ) OPCODE(FPVectorRSqrtEstimate16, U128, U128, U1 )
OPCODE(FPVectorRSqrtEstimate32, U128, U128 ) OPCODE(FPVectorRSqrtEstimate32, U128, U128, U1 )
OPCODE(FPVectorRSqrtEstimate64, U128, U128 ) OPCODE(FPVectorRSqrtEstimate64, U128, U128, U1 )
OPCODE(FPVectorRSqrtStepFused16, U128, U128, U128, U1 ) OPCODE(FPVectorRSqrtStepFused16, U128, U128, U128, U1 )
OPCODE(FPVectorRSqrtStepFused32, U128, U128, U128, U1 ) OPCODE(FPVectorRSqrtStepFused32, U128, U128, U128, U1 )
OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128, U1 ) OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128, U1 )

2
tests/A32/fuzz_arm.cpp
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@ -111,7 +111,7 @@ u32 GenRandomInst(u32 pc, bool is_last_inst) {
// FPSCR is inaccurate // FPSCR is inaccurate
"vfp_VMRS", "vfp_VMRS",
// Unimplemented in Unicorn // Unimplemented in Unicorn
"asimd_VPADD_float", "asimd_VRECPE", "asimd_VPADD_float", "asimd_VRECPE", "asimd_VRSQRTE",
// Incorrect Unicorn implementations // Incorrect Unicorn implementations
"asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. "asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
"asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. "asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.