From 92cb4a5a34f7e4cade91f485aac9b31a1e9d5b56 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 20 Jun 2020 15:13:18 +0100 Subject: [PATCH] A32: Implement ASIMD VRSQRTE --- .../x64/emit_x64_vector_floating_point.cpp | 2 +- src/frontend/A32/decoder/asimd.inc | 2 +- .../translate/impl/asimd_two_regs_misc.cpp | 26 +++++++++++++++++++ .../A32/translate/impl/translate_arm.h | 1 + src/frontend/ir/ir_emitter.cpp | 8 +++--- src/frontend/ir/ir_emitter.h | 2 +- src/frontend/ir/opcodes.inc | 6 ++--- tests/A32/fuzz_arm.cpp | 2 +- 8 files changed, 38 insertions(+), 11 deletions(-) diff --git a/src/backend/x64/emit_x64_vector_floating_point.cpp b/src/backend/x64/emit_x64_vector_floating_point.cpp index 154e12cc..fb49155f 100644 --- a/src/backend/x64/emit_x64_vector_floating_point.cpp +++ b/src/backend/x64/emit_x64_vector_floating_point.cpp @@ -1304,7 +1304,7 @@ void EmitX64::EmitFPVectorRoundInt64(EmitContext& ctx, IR::Inst* inst) { template static void EmitRSqrtEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { - EmitTwoOpFallback(code, ctx, inst, [](VectorArray& result, const VectorArray& operand, FP::FPCR fpcr, FP::FPSR& fpsr) { + EmitTwoOpFallback(code, ctx, inst, [](VectorArray& result, const VectorArray& operand, FP::FPCR fpcr, FP::FPSR& fpsr) { for (size_t i = 0; i < result.size(); i++) { result[i] = FP::FPRSqrtEstimate(operand[i], fpcr, fpsr); } diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 458e8979..0386bd2e 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -104,7 +104,7 @@ INST(asimd_VSWP, "VSWP", "111100111D110010dddd000 //INST(asimd_VSHLL_max, "VSHLL_max", "111100111-11--10----001100-0----") // ASIMD //INST(asimd_VCVT_half, "VCVT (half-precision)", "111100111-11--10----011x00-0----") // ASIMD INST(asimd_VRECPE, "VRECPE", "111100111D11zz11dddd010F0QM0mmmm") // ASIMD -//INST(asimd_VRSQRTE, "VRSQRTE", "111100111-11--11----010x1x-0----") // ASIMD +INST(asimd_VRSQRTE, "VRSQRTE", "111100111D11zz11dddd010F1QM0mmmm") // ASIMD //INST(asimd_VCVT_integer, "VCVT (integer)", "111100111-11--11----011xxx-0----") // ASIMD // One register and modified immediate diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index 870ed77f..39a5870a 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -379,4 +379,30 @@ bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bo return true; } +bool ArmTranslatorVisitor::asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { + if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + return UndefinedInstruction(); + } + + if (sz == 0b00 || sz == 0b11) { + return UndefinedInstruction(); + } + + if (!F && sz == 0b01) { + // TODO: Implement 16-bit VectorUnsignedRecipEstimate + return UndefinedInstruction(); + } + + const size_t esize = 8U << sz; + + const auto d = ToVector(Q, Vd, D); + const auto m = ToVector(Q, Vm, M); + const auto reg_m = ir.GetVector(m); + const auto result = F ? ir.FPVectorRSqrtEstimate(esize, reg_m, false) + : ir.VectorUnsignedRecipSqrtEstimate(reg_m); + + ir.SetVector(d, result); + return true; +} + } // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index af6c6a12..aef984a6 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -500,6 +500,7 @@ struct ArmTranslatorVisitor final { bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm); bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); + bool asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm); // Advanced SIMD load/store structures bool v8_VST_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m); diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index e3fd1807..69684973 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -2479,14 +2479,14 @@ U128 IREmitter::FPVectorRoundInt(size_t esize, const U128& operand, FP::Rounding UNREACHABLE(); } -U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) { +U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a, bool fpcr_controlled) { switch (esize) { case 16: - return Inst(Opcode::FPVectorRSqrtEstimate16, a); + return Inst(Opcode::FPVectorRSqrtEstimate16, a, Imm1(fpcr_controlled)); case 32: - return Inst(Opcode::FPVectorRSqrtEstimate32, a); + return Inst(Opcode::FPVectorRSqrtEstimate32, a, Imm1(fpcr_controlled)); case 64: - return Inst(Opcode::FPVectorRSqrtEstimate64, a); + return Inst(Opcode::FPVectorRSqrtEstimate64, a, Imm1(fpcr_controlled)); } UNREACHABLE(); } diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 3b0052bc..0311d057 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -363,7 +363,7 @@ public: U128 FPVectorRecipEstimate(size_t esize, const U128& a, bool fpcr_controlled = true); U128 FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); U128 FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact); - U128 FPVectorRSqrtEstimate(size_t esize, const U128& a); + U128 FPVectorRSqrtEstimate(size_t esize, const U128& a, bool fpcr_controlled = true); U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); U128 FPVectorSqrt(size_t esize, const U128& a); U128 FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index 3b7cdd0d..d94fe7bd 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -622,9 +622,9 @@ OPCODE(FPVectorRecipStepFused64, U128, U128 OPCODE(FPVectorRoundInt16, U128, U128, U8, U1 ) OPCODE(FPVectorRoundInt32, U128, U128, U8, U1 ) OPCODE(FPVectorRoundInt64, U128, U128, U8, U1 ) -OPCODE(FPVectorRSqrtEstimate16, U128, U128 ) -OPCODE(FPVectorRSqrtEstimate32, U128, U128 ) -OPCODE(FPVectorRSqrtEstimate64, U128, U128 ) +OPCODE(FPVectorRSqrtEstimate16, U128, U128, U1 ) +OPCODE(FPVectorRSqrtEstimate32, U128, U128, U1 ) +OPCODE(FPVectorRSqrtEstimate64, U128, U128, U1 ) OPCODE(FPVectorRSqrtStepFused16, U128, U128, U128, U1 ) OPCODE(FPVectorRSqrtStepFused32, U128, U128, U128, U1 ) OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128, U1 ) diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index e10a3fbe..ebdf506b 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -111,7 +111,7 @@ u32 GenRandomInst(u32 pc, bool is_last_inst) { // FPSCR is inaccurate "vfp_VMRS", // Unimplemented in Unicorn - "asimd_VPADD_float", "asimd_VRECPE", + "asimd_VPADD_float", "asimd_VRECPE", "asimd_VRSQRTE", // Incorrect Unicorn implementations "asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP. "asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.