suyu/dynarmic
28
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)

Browse source
This commit is contained in:
MerryMage 2018-02-13 19:01:21 +00:00
parent 7f68d556ab
commit 8cebb87d0d
2 changed files with 48 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/frontend/A64/decoder/a64.inc
View file

@ -573,9 +573,9 @@ INST(INS_elt, "INS (element)", "01101
INST(CNT, "CNT", "0Q001110zz100000010110nnnnnddddd")
//INST(SADALP, "SADALP", "0Q001110zz100000011010nnnnnddddd")
//INST(SQABS_2, "SQABS", "0Q001110zz100000011110nnnnnddddd")
//INST(CMGT_zero_2, "CMGT (zero)", "0Q001110zz100000100010nnnnnddddd")
//INST(CMEQ_zero_2, "CMEQ (zero)", "0Q001110zz100000100110nnnnnddddd")
//INST(CMLT_2, "CMLT (zero)", "0Q001110zz100000101010nnnnnddddd")
INST(CMGT_zero_2, "CMGT (zero)", "0Q001110zz100000100010nnnnnddddd")
INST(CMEQ_zero_2, "CMEQ (zero)", "0Q001110zz100000100110nnnnnddddd")
INST(CMLT_2, "CMLT (zero)", "0Q001110zz100000101010nnnnnddddd")
//INST(ABS_2, "ABS", "0Q001110zz100000101110nnnnnddddd")
INST(XTN, "XTN, XTN2", "0Q001110zz100001001010nnnnnddddd")
//INST(SQXTN_2, "SQXTN, SQXTN2", "0Q001110zz100001010010nnnnnddddd")

45
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -21,6 +21,51 @@ bool TranslatorVisitor::CNT(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::CMGT_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 zero = ir.ZeroExtendToQuad(ir.Imm64(0)); // TODO: Optimize
const IR::U128 result = ir.VectorGreaterSigned(esize, operand, zero);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::CMEQ_zero_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 zero = ir.ZeroExtendToQuad(ir.Imm64(0)); // TODO: Optimize
IR::U128 result = ir.VectorEqual(esize, operand, zero);
if (datasize == 64) {
result = ir.VectorZeroUpper(result);
}
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::CMLT_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 zero = ir.ZeroExtendToQuad(ir.Imm64(0)); // TODO: Optimize
const IR::U128 result = ir.VectorLessSigned(esize, operand, zero);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::XTN(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();