A64: Implement URSHR (vector)
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16613ee066
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2 changed files with 30 additions and 1 deletions
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@ -804,7 +804,7 @@ INST(SSHLL, "SSHLL, SSHLL2", "0Q001
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//INST(FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd")
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INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd")
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INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd")
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//INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd")
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INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd")
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//INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd")
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//INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd")
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//INST(SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd")
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@ -139,6 +139,35 @@ bool TranslatorVisitor::SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd)
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return true;
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}
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static void UnsignedRoundingShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
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const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend());
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const u64 round_value = 1ULL << (shift_amount - 1);
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const IR::U128 operand = v.V(datasize, Vn);
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const IR::U128 round_const = v.ir.VectorBroadcast(esize, v.I(esize, round_value));
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const IR::U128 round_correction = v.ir.VectorEqual(esize, v.ir.VectorAnd(operand, round_const), round_const);
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const IR::U128 result = v.ir.VectorLogicalShiftRight(esize, operand, shift_amount);
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const IR::U128 corrected_result = v.ir.VectorSub(esize, result, round_correction);
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v.V(datasize, Vd, corrected_result);
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}
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bool TranslatorVisitor::URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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}
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if (!Q && immh.Bit<3>()) {
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return ReservedValue();
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}
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UnsignedRoundingShiftRight(*this, Q, immh, immb, Vn, Vd);
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return true;
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}
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bool TranslatorVisitor::USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (immh == 0b0000) {
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return DecodeError();
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