From 8afdf4b23d4a6682e166eec12b806544aeb27bdc Mon Sep 17 00:00:00 2001 From: Lioncash Date: Wed, 4 Apr 2018 08:36:02 -0400 Subject: [PATCH] A64: Implement URSHR (vector) --- src/frontend/A64/decoder/a64.inc | 2 +- .../impl/simd_shift_by_immediate.cpp | 29 +++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 122ed539..112ae67a 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -804,7 +804,7 @@ INST(SSHLL, "SSHLL, SSHLL2", "0Q001 //INST(FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd") INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd") INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd") -//INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd") +INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd") //INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd") //INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd") //INST(SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp index 06bc7475..a13c136a 100644 --- a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp +++ b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp @@ -139,6 +139,35 @@ bool TranslatorVisitor::SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) return true; } +static void UnsignedRoundingShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { + const size_t datasize = Q ? 128 : 64; + const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const u8 shift_amount = static_cast((esize * 2) - concatenate(immh, immb).ZeroExtend()); + const u64 round_value = 1ULL << (shift_amount - 1); + + const IR::U128 operand = v.V(datasize, Vn); + const IR::U128 round_const = v.ir.VectorBroadcast(esize, v.I(esize, round_value)); + const IR::U128 round_correction = v.ir.VectorEqual(esize, v.ir.VectorAnd(operand, round_const), round_const); + + const IR::U128 result = v.ir.VectorLogicalShiftRight(esize, operand, shift_amount); + const IR::U128 corrected_result = v.ir.VectorSub(esize, result, round_correction); + + v.V(datasize, Vd, corrected_result); +} + +bool TranslatorVisitor::URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { + if (immh == 0b0000) { + return DecodeError(); + } + + if (!Q && immh.Bit<3>()) { + return ReservedValue(); + } + + UnsignedRoundingShiftRight(*this, Q, immh, immb, Vn, Vd); + return true; +} + bool TranslatorVisitor::USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { if (immh == 0b0000) { return DecodeError();