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A64: Implement URSHR (vector)

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Lioncash 2018-04-04 08:36:02 -04:00 committed by MerryMage
parent 16613ee066
commit 8afdf4b23d
2 changed files with 30 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -804,7 +804,7 @@ INST(SSHLL, "SSHLL, SSHLL2", "0Q001
//INST(FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd") //INST(FCVTZS_fix_2, "FCVTZS (vector, fixed-point)", "0Q0011110IIIIiii111111nnnnnddddd")
INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd") INST(USHR_2, "USHR", "0Q1011110IIIIiii000001nnnnnddddd")
INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd") INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd")
//INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd") INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd")
//INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd") //INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd")
//INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd") //INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd")
//INST(SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd") //INST(SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd")

29
src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
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@ -139,6 +139,35 @@ bool TranslatorVisitor::SSHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd)
return true; return true;
} }
static void UnsignedRoundingShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend());
const u64 round_value = 1ULL << (shift_amount - 1);
const IR::U128 operand = v.V(datasize, Vn);
const IR::U128 round_const = v.ir.VectorBroadcast(esize, v.I(esize, round_value));
const IR::U128 round_correction = v.ir.VectorEqual(esize, v.ir.VectorAnd(operand, round_const), round_const);
const IR::U128 result = v.ir.VectorLogicalShiftRight(esize, operand, shift_amount);
const IR::U128 corrected_result = v.ir.VectorSub(esize, result, round_correction);
v.V(datasize, Vd, corrected_result);
}
bool TranslatorVisitor::URSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (immh == 0b0000) {
return DecodeError();
}
if (!Q && immh.Bit<3>()) {
return ReservedValue();
}
UnsignedRoundingShiftRight(*this, Q, immh, immb, Vn, Vd);
return true;
}
bool TranslatorVisitor::USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { bool TranslatorVisitor::USHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (immh == 0b0000) { if (immh == 0b0000) {
return DecodeError(); return DecodeError();