verbose debugging: Ensure host fp state is preserved

This commit is contained in:
Merry 2023-02-03 22:15:53 +00:00
parent fdd5192ab3
commit 890f01f036
4 changed files with 13 additions and 3 deletions

View file

@ -17,6 +17,8 @@ using namespace oaknut::util;
void EmitVerboseDebuggingOutput(oaknut::CodeGenerator& code, EmitContext& ctx) { void EmitVerboseDebuggingOutput(oaknut::CodeGenerator& code, EmitContext& ctx) {
code.SUB(SP, SP, sizeof(RegisterData)); code.SUB(SP, SP, sizeof(RegisterData));
code.MRS(X0, oaknut::SystemReg::FPSR);
code.STR(X0, SP, offsetof(RegisterData, fpsr));
for (int i = 0; i < 30; i++) { for (int i = 0; i < 30; i++) {
if (i == 18) { if (i == 18) {
continue; // Platform register continue; // Platform register
@ -44,6 +46,8 @@ void EmitVerboseDebuggingOutput(oaknut::CodeGenerator& code, EmitContext& ctx) {
} }
code.LDR(oaknut::XReg{i}, SP, offsetof(RegisterData, x) + i * sizeof(u64)); code.LDR(oaknut::XReg{i}, SP, offsetof(RegisterData, x) + i * sizeof(u64));
} }
code.LDR(X0, SP, offsetof(RegisterData, fpsr));
code.MSR(oaknut::SystemReg::FPSR, X0);
code.ADD(SP, SP, sizeof(RegisterData)); code.ADD(SP, SP, sizeof(RegisterData));
} }

View file

@ -46,6 +46,7 @@ struct alignas(16) RegisterData {
std::array<Vector, 32> q; std::array<Vector, 32> q;
u32 nzcv; u32 nzcv;
decltype(StackLayout::spill)* spill; decltype(StackLayout::spill)* spill;
u32 fpsr;
}; };
#ifdef _MSC_VER #ifdef _MSC_VER

View file

@ -105,6 +105,7 @@ void EmitX64::PushRSBHelper(Xbyak::Reg64 loc_desc_reg, Xbyak::Reg64 index_reg, I
void EmitX64::EmitVerboseDebuggingOutput(RegAlloc& reg_alloc, const IR::Block& block) { void EmitX64::EmitVerboseDebuggingOutput(RegAlloc& reg_alloc, const IR::Block& block) {
code.sub(rsp, sizeof(RegisterData)); code.sub(rsp, sizeof(RegisterData));
code.stmxcsr(dword[rsp + offsetof(RegisterData, mxcsr)]);
for (int i = 0; i < 16; i++) { for (int i = 0; i < 16; i++) {
if (rsp.getIdx() == i) { if (rsp.getIdx() == i) {
continue; continue;
@ -128,6 +129,7 @@ void EmitX64::EmitVerboseDebuggingOutput(RegAlloc& reg_alloc, const IR::Block& b
for (int i = 0; i < 16; i++) { for (int i = 0; i < 16; i++) {
code.movaps(Xbyak::Xmm{i}, xword[rsp + offsetof(RegisterData, xmms) + 2 * sizeof(u64) * i]); code.movaps(Xbyak::Xmm{i}, xword[rsp + offsetof(RegisterData, xmms) + 2 * sizeof(u64) * i]);
} }
code.ldmxcsr(dword[rsp + offsetof(RegisterData, mxcsr)]);
code.add(rsp, sizeof(RegisterData)); code.add(rsp, sizeof(RegisterData));
} }
@ -398,7 +400,9 @@ void EmitX64::ClearCache() {
void EmitX64::InvalidateBasicBlocks(const tsl::robin_set<IR::LocationDescriptor>& locations) { void EmitX64::InvalidateBasicBlocks(const tsl::robin_set<IR::LocationDescriptor>& locations) {
code.EnableWriting(); code.EnableWriting();
SCOPE_EXIT { code.DisableWriting(); }; SCOPE_EXIT {
code.DisableWriting();
};
for (const auto& descriptor : locations) { for (const auto& descriptor : locations) {
const auto it = block_descriptors.find(descriptor); const auto it = block_descriptors.find(descriptor);

View file

@ -25,6 +25,7 @@ struct alignas(16) RegisterData {
std::array<u64, 16> gprs; std::array<u64, 16> gprs;
std::array<Vector, 16> xmms; std::array<Vector, 16> xmms;
decltype(StackLayout::spill)* spill; decltype(StackLayout::spill)* spill;
u32 mxcsr;
}; };
#ifdef _MSC_VER #ifdef _MSC_VER