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A32: Implement ASIMD VQSHRN

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Lioncash 2020-06-21 17:39:06 -04:00 committed by merry
parent 85222e3e65
commit 86b0e5c1c5
3 changed files with 7 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -91,7 +91,7 @@ INST(asimd_VSHRN, "VSHRN", "111100101Diiiiiidddd100
//INST(asimd_VRSHRN, "VRSHRN", "111100101-vvv-------100001-1----") // ASIMD
INST(asimd_VQSHRUN, "VQSHRUN", "111100111Diiiiiidddd100000M1mmmm") // ASIMD
INST(asimd_VQRSHRUN, "VQRSHRUN", "111100111Diiiiiidddd100001M1mmmm") // ASIMD
//INST(asimd_VQSHRN, "VQSHRN", "1111001U1-vvv-------100100-1----") // ASIMD
INST(asimd_VQSHRN, "VQSHRN", "1111001U1Diiiiiidddd100100M1mmmm") // ASIMD
INST(asimd_VQRSHRN, "VQRSHRN", "1111001U1Diiiiiidddd100101M1mmmm") // ASIMD
//INST(asimd_SHLL, "SHLL", "1111001U1-vvv-------101000-1----") // ASIMD
INST(asimd_VCVT_fixed, "VCVT (fixed-point)", "1111001U1Diiiiiidddd111o0QM1mmmm") // ASIMD

5
src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
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@ -291,6 +291,11 @@ bool ArmTranslatorVisitor::asimd_VQSHRUN(bool D, size_t imm6, size_t Vd, bool M,
Rounding::None, Narrowing::SaturateToUnsigned, Signedness::Signed);
}
bool ArmTranslatorVisitor::asimd_VQSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) {
return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm,
Rounding::None, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed);
}
bool ArmTranslatorVisitor::asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) {
return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm,
Rounding::Round, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed);

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -517,6 +517,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VQSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VQSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VCVT_fixed(bool U, bool D, size_t imm6, size_t Vd, bool to_fixed, bool Q, bool M, size_t Vm);