From 86b0e5c1c5564e41c8303aecda0ed9c338c18cfa Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 21 Jun 2020 17:39:06 -0400 Subject: [PATCH] A32: Implement ASIMD VQSHRN --- src/frontend/A32/decoder/asimd.inc | 2 +- src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp | 5 +++++ src/frontend/A32/translate/impl/translate_arm.h | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 62f5a299..56287bbe 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -91,7 +91,7 @@ INST(asimd_VSHRN, "VSHRN", "111100101Diiiiiidddd100 //INST(asimd_VRSHRN, "VRSHRN", "111100101-vvv-------100001-1----") // ASIMD INST(asimd_VQSHRUN, "VQSHRUN", "111100111Diiiiiidddd100000M1mmmm") // ASIMD INST(asimd_VQRSHRUN, "VQRSHRUN", "111100111Diiiiiidddd100001M1mmmm") // ASIMD -//INST(asimd_VQSHRN, "VQSHRN", "1111001U1-vvv-------100100-1----") // ASIMD +INST(asimd_VQSHRN, "VQSHRN", "1111001U1Diiiiiidddd100100M1mmmm") // ASIMD INST(asimd_VQRSHRN, "VQRSHRN", "1111001U1Diiiiiidddd100101M1mmmm") // ASIMD //INST(asimd_SHLL, "SHLL", "1111001U1-vvv-------101000-1----") // ASIMD INST(asimd_VCVT_fixed, "VCVT (fixed-point)", "1111001U1Diiiiiidddd111o0QM1mmmm") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp index 518c7c57..e6256428 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp @@ -291,6 +291,11 @@ bool ArmTranslatorVisitor::asimd_VQSHRUN(bool D, size_t imm6, size_t Vd, bool M, Rounding::None, Narrowing::SaturateToUnsigned, Signedness::Signed); } +bool ArmTranslatorVisitor::asimd_VQSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { + return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, + Rounding::None, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed); +} + bool ArmTranslatorVisitor::asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, Rounding::Round, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index fa2fe7ae..947de032 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -517,6 +517,7 @@ struct ArmTranslatorVisitor final { bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VQSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); + bool asimd_VQSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VCVT_fixed(bool U, bool D, size_t imm6, size_t Vd, bool to_fixed, bool Q, bool M, size_t Vm);