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backend/arm64: Implement A32SetCheckBit

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Merry 2022-07-22 15:04:31 +01:00 committed by merry
parent 3e5309bd96
commit 84cad9f831
2 changed files with 12 additions and 0 deletions
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2
src/dynarmic/backend/arm64/emit_arm64.cpp
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@ -25,6 +25,8 @@ void EmitIR(oaknut::CodeGenerator&, EmitContext&, IR::Inst*) {
ASSERT_FALSE("Unimplemented opcode {}", op); ASSERT_FALSE("Unimplemented opcode {}", op);
} }
template<>
void EmitIR<IR::Opcode::A32SetCheckBit>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst);
template<> template<>
void EmitIR<IR::Opcode::A32GetRegister>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst); void EmitIR<IR::Opcode::A32GetRegister>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst);
template<> template<>

10
src/dynarmic/backend/arm64/emit_arm64_a32.cpp
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@ -122,6 +122,16 @@ void EmitA32Terminal(oaknut::CodeGenerator& code, EmitContext& ctx) {
EmitA32Terminal(code, ctx, ctx.block.GetTerminal(), location.SetSingleStepping(false), location.SingleStepping()); EmitA32Terminal(code, ctx, ctx.block.GetTerminal(), location.SetSingleStepping(false), location.SingleStepping());
} }
template<>
void EmitIR<IR::Opcode::A32SetCheckBit>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
auto Wbit = ctx.reg_alloc.ReadW(args[0]);
RegAlloc::Realize(Wbit);
code.STRB(Wbit, SP, offsetof(StackLayout, check_bit));
}
template<> template<>
void EmitIR<IR::Opcode::A32GetRegister>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::A32GetRegister>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
const A32::Reg reg = inst->GetArg(0).GetA32RegRef(); const A32::Reg reg = inst->GetArg(0).GetA32RegRef();