diff --git a/src/dynarmic/backend/arm64/emit_arm64.cpp b/src/dynarmic/backend/arm64/emit_arm64.cpp
index 3424c28f..fd3a324c 100644
--- a/src/dynarmic/backend/arm64/emit_arm64.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64.cpp
@@ -25,6 +25,8 @@ void EmitIR(oaknut::CodeGenerator&, EmitContext&, IR::Inst*) {
     ASSERT_FALSE("Unimplemented opcode {}", op);
 }
 
+template<>
+void EmitIR<IR::Opcode::A32SetCheckBit>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst);
 template<>
 void EmitIR<IR::Opcode::A32GetRegister>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst);
 template<>
diff --git a/src/dynarmic/backend/arm64/emit_arm64_a32.cpp b/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
index b732caf6..c98ca70b 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_a32.cpp
@@ -122,6 +122,16 @@ void EmitA32Terminal(oaknut::CodeGenerator& code, EmitContext& ctx) {
     EmitA32Terminal(code, ctx, ctx.block.GetTerminal(), location.SetSingleStepping(false), location.SingleStepping());
 }
 
+template<>
+void EmitIR<IR::Opcode::A32SetCheckBit>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
+    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
+
+    auto Wbit = ctx.reg_alloc.ReadW(args[0]);
+    RegAlloc::Realize(Wbit);
+
+    code.STRB(Wbit, SP, offsetof(StackLayout, check_bit));
+}
+
 template<>
 void EmitIR<IR::Opcode::A32GetRegister>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     const A32::Reg reg = inst->GetArg(0).GetA32RegRef();