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Remove ChangeProcessorID hack

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* No library users require this hack any longer.
This commit is contained in:
MerryMage 2021-05-01 20:31:56 +01:00
parent 6404f58d23
commit 795b9bea9a
6 changed files with 4 additions and 36 deletions
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3
include/dynarmic/A32/a32.h
View file

@ -66,9 +66,6 @@ public:
*/ */
void ExceptionalExit(); void ExceptionalExit();
/// HACK: Change processor ID.
void ChangeProcessorID(std::size_t new_processor);
/// View and modify registers. /// View and modify registers.
std::array<std::uint32_t, 16>& Regs(); std::array<std::uint32_t, 16>& Regs();
const std::array<std::uint32_t, 16>& Regs() const; const std::array<std::uint32_t, 16>& Regs() const;

3
include/dynarmic/A64/a64.h
View file

@ -67,9 +67,6 @@ public:
*/ */
void ExceptionalExit(); void ExceptionalExit();
/// HACK: Change processor ID.
void ChangeProcessorID(std::size_t new_processor);
/// Read Stack Pointer /// Read Stack Pointer
std::uint64_t GetSP() const; std::uint64_t GetSP() const;
/// Modify Stack Pointer /// Modify Stack Pointer

6
src/backend/x64/a32_emit_x64.h
View file

@ -55,12 +55,8 @@ public:
void InvalidateCacheRanges(const boost::icl::interval_set<u32>& ranges); void InvalidateCacheRanges(const boost::icl::interval_set<u32>& ranges);
void ChangeProcessorID(size_t value) {
conf.processor_id = value;
}
protected: protected:
A32::UserConfig conf; const A32::UserConfig conf;
A32::Jit* jit_interface; A32::Jit* jit_interface;
BlockRangeInformation<u32> block_ranges; BlockRangeInformation<u32> block_ranges;

11
src/backend/x64/a32_interface.cpp
View file

@ -63,7 +63,7 @@ struct Jit::Impl {
BlockOfCode block_of_code; BlockOfCode block_of_code;
A32EmitX64 emitter; A32EmitX64 emitter;
A32::UserConfig conf; const A32::UserConfig conf;
// Requests made during execution to invalidate the cache are queued up here. // Requests made during execution to invalidate the cache are queued up here.
size_t invalid_cache_generation = 0; size_t invalid_cache_generation = 0;
@ -98,11 +98,6 @@ struct Jit::Impl {
PerformCacheInvalidation(); PerformCacheInvalidation();
} }
void ChangeProcessorID(size_t value) {
conf.processor_id = value;
emitter.ChangeProcessorID(value);
}
void ClearExclusiveState() { void ClearExclusiveState() {
jit_state.exclusive_state = 0; jit_state.exclusive_state = 0;
} }
@ -247,10 +242,6 @@ void Jit::ClearExclusiveState() {
impl->ClearExclusiveState(); impl->ClearExclusiveState();
} }
void Jit::ChangeProcessorID(size_t new_processor) {
impl->ChangeProcessorID(new_processor);
}
std::array<u32, 16>& Jit::Regs() { std::array<u32, 16>& Jit::Regs() {
return impl->jit_state.Reg; return impl->jit_state.Reg;
} }

6
src/backend/x64/a64_emit_x64.h
View file

@ -51,12 +51,8 @@ public:
void InvalidateCacheRanges(const boost::icl::interval_set<u64>& ranges); void InvalidateCacheRanges(const boost::icl::interval_set<u64>& ranges);
void ChangeProcessorID(size_t value) {
conf.processor_id = value;
}
protected: protected:
A64::UserConfig conf; const A64::UserConfig conf;
A64::Jit* jit_interface; A64::Jit* jit_interface;
BlockRangeInformation<u64> block_ranges; BlockRangeInformation<u64> block_ranges;

11
src/backend/x64/a64_interface.cpp
View file

@ -97,11 +97,6 @@ public:
is_executing = false; is_executing = false;
} }
void ChangeProcessorID(size_t value) {
conf.processor_id = value;
emitter.ChangeProcessorID(value);
}
void ClearCache() { void ClearCache() {
invalidate_entire_cache = true; invalidate_entire_cache = true;
RequestCacheInvalidation(); RequestCacheInvalidation();
@ -292,7 +287,7 @@ private:
bool is_executing = false; bool is_executing = false;
UserConfig conf; const UserConfig conf;
A64JitState jit_state; A64JitState jit_state;
BlockOfCode block_of_code; BlockOfCode block_of_code;
A64EmitX64 emitter; A64EmitX64 emitter;
@ -334,10 +329,6 @@ void Jit::ExceptionalExit() {
impl->ExceptionalExit(); impl->ExceptionalExit();
} }
void Jit::ChangeProcessorID(size_t new_processor) {
impl->ChangeProcessorID(new_processor);
}
u64 Jit::GetSP() const { u64 Jit::GetSP() const {
return impl->GetSP(); return impl->GetSP();
} }