suyu/dynarmic
28
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)

Browse source
This commit is contained in:
MerryMage 2016-08-06 20:42:06 +01:00
parent 4d127c19dd
commit 7915f97d98
1 changed files with 6 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/frontend/translate/translate_arm/load_store.cpp
View file

@ -115,13 +115,15 @@ bool ArmTranslatorVisitor::arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n
auto data_a = ir.ReadMemory32(address_a); auto data_a = ir.ReadMemory32(address_a);
auto data_b = ir.ReadMemory32(address_b); auto data_b = ir.ReadMemory32(address_b);
switch(d) { switch (d) {
case Reg::PC: case Reg::PC:
data_a = ir.Add(data_a, ir.Imm32(4)); data_a = ir.Add(data_a, ir.Imm32(4));
break; break;
case Reg::LR: case Reg::LR:
data_b = ir.Add(data_b, ir.Imm32(4)); data_b = ir.Add(data_b, ir.Imm32(4));
break; break;
default:
break;
} }
if (d == Reg::PC) { if (d == Reg::PC) {
@ -153,13 +155,15 @@ bool ArmTranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n
auto data_a = ir.ReadMemory32(address_a); auto data_a = ir.ReadMemory32(address_a);
auto data_b = ir.ReadMemory32(address_b); auto data_b = ir.ReadMemory32(address_b);
switch(d) { switch (d) {
case Reg::PC: case Reg::PC:
data_a = ir.Add(data_a, ir.Imm32(4)); data_a = ir.Add(data_a, ir.Imm32(4));
break; break;
case Reg::LR: case Reg::LR:
data_b = ir.Add(data_b, ir.Imm32(4)); data_b = ir.Add(data_b, ir.Imm32(4));
break; break;
default:
break;
} }
if (d == Reg::PC) { if (d == Reg::PC) {