From 7915f97d98b88e88b76a4e7f07a38b220504a9e4 Mon Sep 17 00:00:00 2001
From: MerryMage <MerryMage@users.noreply.github.com>
Date: Sat, 6 Aug 2016 20:42:06 +0100
Subject: [PATCH] TranslateArm/LoadStore: Add default case to switches for
 arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)

---
 src/frontend/translate/translate_arm/load_store.cpp | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/frontend/translate/translate_arm/load_store.cpp b/src/frontend/translate/translate_arm/load_store.cpp
index 4ea1f12f..2237ea47 100644
--- a/src/frontend/translate/translate_arm/load_store.cpp
+++ b/src/frontend/translate/translate_arm/load_store.cpp
@@ -115,13 +115,15 @@ bool ArmTranslatorVisitor::arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n
         auto data_a = ir.ReadMemory32(address_a);
         auto data_b = ir.ReadMemory32(address_b);
 
-        switch(d) {
+        switch (d) {
         case Reg::PC:
             data_a = ir.Add(data_a, ir.Imm32(4));
             break;
         case Reg::LR:
             data_b = ir.Add(data_b, ir.Imm32(4));
             break;
+        default:
+            break;
         }
 
         if (d == Reg::PC) {
@@ -153,13 +155,15 @@ bool ArmTranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n
         auto data_a = ir.ReadMemory32(address_a);
         auto data_b = ir.ReadMemory32(address_b);
 
-        switch(d) {
+        switch (d) {
         case Reg::PC:
             data_a = ir.Add(data_a, ir.Imm32(4));
             break;
         case Reg::LR:
             data_b = ir.Add(data_b, ir.Imm32(4));
             break;
+        default:
+            break;
         }
 
         if (d == Reg::PC) {