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General: Correct typos is code comments

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Lioncash 2019-05-24 01:37:03 -04:00 committed by MerryMage
parent 6187de7ca7
commit 6b9bf7868a
13 changed files with 16 additions and 16 deletions
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2
include/dynarmic/A32/config.h
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@ -69,7 +69,7 @@ struct UserCallbacks {
// A conservative implementation that always returns false is safe. // A conservative implementation that always returns false is safe.
virtual bool IsReadOnlyMemory(VAddr /* vaddr */) { return false; } virtual bool IsReadOnlyMemory(VAddr /* vaddr */) { return false; }
/// The intrepreter must execute exactly num_instructions starting from PC. /// The interpreter must execute exactly num_instructions starting from PC.
virtual void InterpreterFallback(VAddr pc, size_t num_instructions) = 0; virtual void InterpreterFallback(VAddr pc, size_t num_instructions) = 0;
// This callback is called whenever a SVC instruction is executed. // This callback is called whenever a SVC instruction is executed.

4
include/dynarmic/A64/config.h
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@ -90,7 +90,7 @@ struct UserCallbacks {
// A conservative implementation that always returns false is safe. // A conservative implementation that always returns false is safe.
virtual bool IsReadOnlyMemory(VAddr /* vaddr */) { return false; } virtual bool IsReadOnlyMemory(VAddr /* vaddr */) { return false; }
/// The intrepreter must execute exactly num_instructions starting from PC. /// The interpreter must execute exactly num_instructions starting from PC.
virtual void InterpreterFallback(VAddr pc, size_t num_instructions) = 0; virtual void InterpreterFallback(VAddr pc, size_t num_instructions) = 0;
// This callback is called whenever a SVC instruction is executed. // This callback is called whenever a SVC instruction is executed.
@ -128,7 +128,7 @@ struct UserConfig {
/// CTR_EL0<27:24> is log2 of the cache writeback granule in words. /// CTR_EL0<27:24> is log2 of the cache writeback granule in words.
/// CTR_EL0<23:20> is log2 of the exclusives reservation granule in words. /// CTR_EL0<23:20> is log2 of the exclusives reservation granule in words.
/// CTR_EL0<19:16> is log2 of the smallest data/unifed cacheline in words. /// CTR_EL0<19:16> is log2 of the smallest data/unified cacheline in words.
/// CTR_EL0<15:14> is the level 1 instruction cache policy. /// CTR_EL0<15:14> is the level 1 instruction cache policy.
/// CTR_EL0<3:0> is log2 of the smallest instruction cacheline in words. /// CTR_EL0<3:0> is log2 of the smallest instruction cacheline in words.
std::uint32_t ctr_el0 = 0x8444c004; std::uint32_t ctr_el0 = 0x8444c004;

2
src/backend/x64/a32_emit_x64.cpp
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@ -923,7 +923,7 @@ static void ExclusiveWrite(BlockOfCode& code, RegAlloc& reg_alloc, IR::Inst* ins
reg_alloc.HostCall(nullptr, {}, args[0], args[1]); reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
} }
const Xbyak::Reg32 passed = reg_alloc.ScratchGpr().cvt32(); const Xbyak::Reg32 passed = reg_alloc.ScratchGpr().cvt32();
const Xbyak::Reg32 tmp = code.ABI_RETURN.cvt32(); // Use one of the unusued HostCall registers. const Xbyak::Reg32 tmp = code.ABI_RETURN.cvt32(); // Use one of the unused HostCall registers.
Xbyak::Label end; Xbyak::Label end;

2
src/backend/x64/a32_jitstate.cpp
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@ -155,7 +155,7 @@ void A32JitState::ResetRSB() {
* Len bits 16-18 Vector length * Len bits 16-18 Vector length
*/ */
// NZCV; QC (ASMID only), AHP; DN, FZ, RMode, Stride; SBZP; Len; trap enables; cumulative bits // NZCV; QC (ASIMD only), AHP; DN, FZ, RMode, Stride; SBZP; Len; trap enables; cumulative bits
constexpr u32 FPSCR_MODE_MASK = A32::LocationDescriptor::FPSCR_MODE_MASK; constexpr u32 FPSCR_MODE_MASK = A32::LocationDescriptor::FPSCR_MODE_MASK;
constexpr u32 FPSCR_NZCV_MASK = 0xF0000000; constexpr u32 FPSCR_NZCV_MASK = 0xF0000000;

2
src/backend/x64/emit_x64_crc32.cpp
View file

@ -1,7 +1,7 @@
/* This file is part of the dynarmic project. /* This file is part of the dynarmic project.
* Copyright (c) 2018 MerryMage * Copyright (c) 2018 MerryMage
* This software may be used and distributed according to the terms of the GNU * This software may be used and distributed according to the terms of the GNU
* General Public icense version 2 or any later version. * General Public License version 2 or any later version.
*/ */
#include <array> #include <array>

2
src/backend/x64/emit_x64_sm4.cpp
View file

@ -1,7 +1,7 @@
/* This file is part of the dynarmic project. /* This file is part of the dynarmic project.
* Copyright (c) 2018 MerryMage * Copyright (c) 2018 MerryMage
* This software may be used and distributed according to the terms of the GNU * This software may be used and distributed according to the terms of the GNU
* General Public icense version 2 or any later version. * General Public License version 2 or any later version.
*/ */
#include "backend/x64/block_of_code.h" #include "backend/x64/block_of_code.h"

2
src/frontend/A32/translate/impl/vfp.cpp
View file

@ -44,7 +44,7 @@ bool ArmTranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, E
// The VFP register file is divided into banks each containing: // The VFP register file is divided into banks each containing:
// * eight single-precision registers, or // * eight single-precision registers, or
// * four double-precision reigsters. // * four double-precision registers.
// VFP vector instructions access these registers in a circular manner. // VFP vector instructions access these registers in a circular manner.
const auto bank_increment = [register_bank_size](ExtReg reg, size_t stride) -> ExtReg { const auto bank_increment = [register_bank_size](ExtReg reg, size_t stride) -> ExtReg {
const auto reg_number = static_cast<size_t>(reg); const auto reg_number = static_cast<size_t>(reg);

2
src/frontend/A32/translate/translate_thumb.cpp
View file

@ -134,4 +134,4 @@ bool ThumbTranslatorVisitor::RaiseException(Exception exception) {
return false; return false;
} }
} // namepsace Dynarmic::A32 } // namespace Dynarmic::A32

4
src/frontend/A64/decoder/a64.inc
View file

@ -101,7 +101,7 @@ INST(DC_CVAU, "DC CVAU", "11010
INST(DC_CVAP, "DC CVAP", "110101010000101101111100001ttttt") INST(DC_CVAP, "DC CVAP", "110101010000101101111100001ttttt")
INST(DC_CIVAC, "DC CIVAC", "110101010000101101111110001ttttt") INST(DC_CIVAC, "DC CIVAC", "110101010000101101111110001ttttt")
// Unconditonal branch (Register) // Unconditional branch (Register)
INST(BLR, "BLR", "1101011000111111000000nnnnn00000") INST(BLR, "BLR", "1101011000111111000000nnnnn00000")
INST(BR, "BR", "1101011000011111000000nnnnn00000") INST(BR, "BR", "1101011000011111000000nnnnn00000")
//INST(DRPS, "DRPS", "11010110101111110000001111100000") //INST(DRPS, "DRPS", "11010110101111110000001111100000")
@ -112,7 +112,7 @@ INST(RET, "RET", "11010
//INST(ERETA, "ERETAA, ERETAB", "110101101001111100001M1111111111") // ARMv8.3 //INST(ERETA, "ERETAA, ERETAB", "110101101001111100001M1111111111") // ARMv8.3
//INST(RETA, "RETAA, RETAB", "110101100101111100001M1111111111") // ARMv8.3 //INST(RETA, "RETAA, RETAB", "110101100101111100001M1111111111") // ARMv8.3
// Unconditonal branch (immediate) // Unconditional branch (immediate)
INST(B_uncond, "B", "000101iiiiiiiiiiiiiiiiiiiiiiiiii") INST(B_uncond, "B", "000101iiiiiiiiiiiiiiiiiiiiiiiiii")
INST(BL, "BL", "100101iiiiiiiiiiiiiiiiiiiiiiiiii") INST(BL, "BL", "100101iiiiiiiiiiiiiiiiiiiiiiiiii")

4
src/frontend/A64/translate/impl/impl.h
View file

@ -176,7 +176,7 @@ struct TranslatorVisitor final {
bool DC_CVAP(Reg Rt); bool DC_CVAP(Reg Rt);
bool DC_CIVAC(Reg Rt); bool DC_CIVAC(Reg Rt);
// Unconditonal branch (Register) // Unconditional branch (Register)
bool BR(Reg Rn); bool BR(Reg Rn);
bool BRA(bool Z, bool M, Reg Rn, Reg Rm); bool BRA(bool Z, bool M, Reg Rn, Reg Rm);
bool BLR(Reg Rn); bool BLR(Reg Rn);
@ -187,7 +187,7 @@ struct TranslatorVisitor final {
bool ERETA(bool M); bool ERETA(bool M);
bool DRPS(); bool DRPS();
// Unconditonal branch (immediate) // Unconditional branch (immediate)
bool B_uncond(Imm<26> imm26); bool B_uncond(Imm<26> imm26);
bool BL(Imm<26> imm26); bool BL(Imm<26> imm26);

2
src/frontend/imm.h
View file

@ -143,7 +143,7 @@ bool operator>=(Imm<bit_size> a, u32 b) {
} }
/** /**
* Concatentate immediates together. * Concatenate immediates together.
* Left to right corresponds to most significant imm to least significant imm. * Left to right corresponds to most significant imm to least significant imm.
* This is equivalent to a:b:...:z in ASL. * This is equivalent to a:b:...:z in ASL.
*/ */

2
src/frontend/ir/basic_block.h
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@ -112,7 +112,7 @@ public:
LocationDescriptor ConditionFailedLocation() const; LocationDescriptor ConditionFailedLocation() const;
/// Sets the location of the block to execute if the predicated condition fails. /// Sets the location of the block to execute if the predicated condition fails.
void SetConditionFailedLocation(LocationDescriptor fail_location); void SetConditionFailedLocation(LocationDescriptor fail_location);
/// Determines whether or not a prediated condition failure block is present. /// Determines whether or not a predicated condition failure block is present.
bool HasConditionFailedLocation() const; bool HasConditionFailedLocation() const;
/// Gets a mutable reference to the condition failed cycle count. /// Gets a mutable reference to the condition failed cycle count.

2
src/frontend/ir/microinstruction.h
View file

@ -109,7 +109,7 @@ public:
/// Pseudo-instructions depend on their parent instructions for their semantics. /// Pseudo-instructions depend on their parent instructions for their semantics.
bool IsAPseudoOperation() const; bool IsAPseudoOperation() const;
/// Determins whether or not this instruction supports the GetNZCVFromOp pseudo-operation. /// Determines whether or not this instruction supports the GetNZCVFromOp pseudo-operation.
bool MayGetNZCVFromOp() const; bool MayGetNZCVFromOp() const;
/// Determines if all arguments of this instruction are immediates. /// Determines if all arguments of this instruction are immediates.