From 6b9bf7868a7e3c4008a54bea1a437f67f7c8c95a Mon Sep 17 00:00:00 2001 From: Lioncash Date: Fri, 24 May 2019 01:37:03 -0400 Subject: [PATCH] General: Correct typos is code comments --- include/dynarmic/A32/config.h | 2 +- include/dynarmic/A64/config.h | 4 ++-- src/backend/x64/a32_emit_x64.cpp | 2 +- src/backend/x64/a32_jitstate.cpp | 2 +- src/backend/x64/emit_x64_crc32.cpp | 2 +- src/backend/x64/emit_x64_sm4.cpp | 2 +- src/frontend/A32/translate/impl/vfp.cpp | 2 +- src/frontend/A32/translate/translate_thumb.cpp | 2 +- src/frontend/A64/decoder/a64.inc | 4 ++-- src/frontend/A64/translate/impl/impl.h | 4 ++-- src/frontend/imm.h | 2 +- src/frontend/ir/basic_block.h | 2 +- src/frontend/ir/microinstruction.h | 2 +- 13 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/dynarmic/A32/config.h b/include/dynarmic/A32/config.h index 1857c1bb..e2824a41 100644 --- a/include/dynarmic/A32/config.h +++ b/include/dynarmic/A32/config.h @@ -69,7 +69,7 @@ struct UserCallbacks { // A conservative implementation that always returns false is safe. virtual bool IsReadOnlyMemory(VAddr /* vaddr */) { return false; } - /// The intrepreter must execute exactly num_instructions starting from PC. + /// The interpreter must execute exactly num_instructions starting from PC. virtual void InterpreterFallback(VAddr pc, size_t num_instructions) = 0; // This callback is called whenever a SVC instruction is executed. diff --git a/include/dynarmic/A64/config.h b/include/dynarmic/A64/config.h index 425004b5..2efc238c 100644 --- a/include/dynarmic/A64/config.h +++ b/include/dynarmic/A64/config.h @@ -90,7 +90,7 @@ struct UserCallbacks { // A conservative implementation that always returns false is safe. virtual bool IsReadOnlyMemory(VAddr /* vaddr */) { return false; } - /// The intrepreter must execute exactly num_instructions starting from PC. + /// The interpreter must execute exactly num_instructions starting from PC. virtual void InterpreterFallback(VAddr pc, size_t num_instructions) = 0; // This callback is called whenever a SVC instruction is executed. @@ -128,7 +128,7 @@ struct UserConfig { /// CTR_EL0<27:24> is log2 of the cache writeback granule in words. /// CTR_EL0<23:20> is log2 of the exclusives reservation granule in words. - /// CTR_EL0<19:16> is log2 of the smallest data/unifed cacheline in words. + /// CTR_EL0<19:16> is log2 of the smallest data/unified cacheline in words. /// CTR_EL0<15:14> is the level 1 instruction cache policy. /// CTR_EL0<3:0> is log2 of the smallest instruction cacheline in words. std::uint32_t ctr_el0 = 0x8444c004; diff --git a/src/backend/x64/a32_emit_x64.cpp b/src/backend/x64/a32_emit_x64.cpp index 43fc30a4..df37fdbb 100644 --- a/src/backend/x64/a32_emit_x64.cpp +++ b/src/backend/x64/a32_emit_x64.cpp @@ -923,7 +923,7 @@ static void ExclusiveWrite(BlockOfCode& code, RegAlloc& reg_alloc, IR::Inst* ins reg_alloc.HostCall(nullptr, {}, args[0], args[1]); } const Xbyak::Reg32 passed = reg_alloc.ScratchGpr().cvt32(); - const Xbyak::Reg32 tmp = code.ABI_RETURN.cvt32(); // Use one of the unusued HostCall registers. + const Xbyak::Reg32 tmp = code.ABI_RETURN.cvt32(); // Use one of the unused HostCall registers. Xbyak::Label end; diff --git a/src/backend/x64/a32_jitstate.cpp b/src/backend/x64/a32_jitstate.cpp index 2676cbc8..57cb0f18 100644 --- a/src/backend/x64/a32_jitstate.cpp +++ b/src/backend/x64/a32_jitstate.cpp @@ -155,7 +155,7 @@ void A32JitState::ResetRSB() { * Len bits 16-18 Vector length */ -// NZCV; QC (ASMID only), AHP; DN, FZ, RMode, Stride; SBZP; Len; trap enables; cumulative bits +// NZCV; QC (ASIMD only), AHP; DN, FZ, RMode, Stride; SBZP; Len; trap enables; cumulative bits constexpr u32 FPSCR_MODE_MASK = A32::LocationDescriptor::FPSCR_MODE_MASK; constexpr u32 FPSCR_NZCV_MASK = 0xF0000000; diff --git a/src/backend/x64/emit_x64_crc32.cpp b/src/backend/x64/emit_x64_crc32.cpp index 20a676c2..91c0239d 100644 --- a/src/backend/x64/emit_x64_crc32.cpp +++ b/src/backend/x64/emit_x64_crc32.cpp @@ -1,7 +1,7 @@ /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * This software may be used and distributed according to the terms of the GNU - * General Public icense version 2 or any later version. + * General Public License version 2 or any later version. */ #include diff --git a/src/backend/x64/emit_x64_sm4.cpp b/src/backend/x64/emit_x64_sm4.cpp index 51507f0d..ada988b4 100644 --- a/src/backend/x64/emit_x64_sm4.cpp +++ b/src/backend/x64/emit_x64_sm4.cpp @@ -1,7 +1,7 @@ /* This file is part of the dynarmic project. * Copyright (c) 2018 MerryMage * This software may be used and distributed according to the terms of the GNU - * General Public icense version 2 or any later version. + * General Public License version 2 or any later version. */ #include "backend/x64/block_of_code.h" diff --git a/src/frontend/A32/translate/impl/vfp.cpp b/src/frontend/A32/translate/impl/vfp.cpp index b98a17c9..ebd1cf1b 100644 --- a/src/frontend/A32/translate/impl/vfp.cpp +++ b/src/frontend/A32/translate/impl/vfp.cpp @@ -44,7 +44,7 @@ bool ArmTranslatorVisitor::EmitVfpVectorOperation(bool sz, ExtReg d, ExtReg n, E // The VFP register file is divided into banks each containing: // * eight single-precision registers, or - // * four double-precision reigsters. + // * four double-precision registers. // VFP vector instructions access these registers in a circular manner. const auto bank_increment = [register_bank_size](ExtReg reg, size_t stride) -> ExtReg { const auto reg_number = static_cast(reg); diff --git a/src/frontend/A32/translate/translate_thumb.cpp b/src/frontend/A32/translate/translate_thumb.cpp index 7fc29cbd..deeb5f76 100644 --- a/src/frontend/A32/translate/translate_thumb.cpp +++ b/src/frontend/A32/translate/translate_thumb.cpp @@ -134,4 +134,4 @@ bool ThumbTranslatorVisitor::RaiseException(Exception exception) { return false; } -} // namepsace Dynarmic::A32 +} // namespace Dynarmic::A32 diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index e35d7f24..23625be7 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -101,7 +101,7 @@ INST(DC_CVAU, "DC CVAU", "11010 INST(DC_CVAP, "DC CVAP", "110101010000101101111100001ttttt") INST(DC_CIVAC, "DC CIVAC", "110101010000101101111110001ttttt") -// Unconditonal branch (Register) +// Unconditional branch (Register) INST(BLR, "BLR", "1101011000111111000000nnnnn00000") INST(BR, "BR", "1101011000011111000000nnnnn00000") //INST(DRPS, "DRPS", "11010110101111110000001111100000") @@ -112,7 +112,7 @@ INST(RET, "RET", "11010 //INST(ERETA, "ERETAA, ERETAB", "110101101001111100001M1111111111") // ARMv8.3 //INST(RETA, "RETAA, RETAB", "110101100101111100001M1111111111") // ARMv8.3 -// Unconditonal branch (immediate) +// Unconditional branch (immediate) INST(B_uncond, "B", "000101iiiiiiiiiiiiiiiiiiiiiiiiii") INST(BL, "BL", "100101iiiiiiiiiiiiiiiiiiiiiiiiii") diff --git a/src/frontend/A64/translate/impl/impl.h b/src/frontend/A64/translate/impl/impl.h index 91b3430b..4c12aa21 100644 --- a/src/frontend/A64/translate/impl/impl.h +++ b/src/frontend/A64/translate/impl/impl.h @@ -176,7 +176,7 @@ struct TranslatorVisitor final { bool DC_CVAP(Reg Rt); bool DC_CIVAC(Reg Rt); - // Unconditonal branch (Register) + // Unconditional branch (Register) bool BR(Reg Rn); bool BRA(bool Z, bool M, Reg Rn, Reg Rm); bool BLR(Reg Rn); @@ -187,7 +187,7 @@ struct TranslatorVisitor final { bool ERETA(bool M); bool DRPS(); - // Unconditonal branch (immediate) + // Unconditional branch (immediate) bool B_uncond(Imm<26> imm26); bool BL(Imm<26> imm26); diff --git a/src/frontend/imm.h b/src/frontend/imm.h index 941374b2..4360a023 100644 --- a/src/frontend/imm.h +++ b/src/frontend/imm.h @@ -143,7 +143,7 @@ bool operator>=(Imm a, u32 b) { } /** - * Concatentate immediates together. + * Concatenate immediates together. * Left to right corresponds to most significant imm to least significant imm. * This is equivalent to a:b:...:z in ASL. */ diff --git a/src/frontend/ir/basic_block.h b/src/frontend/ir/basic_block.h index ca91aacc..c370d1c0 100644 --- a/src/frontend/ir/basic_block.h +++ b/src/frontend/ir/basic_block.h @@ -112,7 +112,7 @@ public: LocationDescriptor ConditionFailedLocation() const; /// Sets the location of the block to execute if the predicated condition fails. void SetConditionFailedLocation(LocationDescriptor fail_location); - /// Determines whether or not a prediated condition failure block is present. + /// Determines whether or not a predicated condition failure block is present. bool HasConditionFailedLocation() const; /// Gets a mutable reference to the condition failed cycle count. diff --git a/src/frontend/ir/microinstruction.h b/src/frontend/ir/microinstruction.h index 6867d8da..54a2dc61 100644 --- a/src/frontend/ir/microinstruction.h +++ b/src/frontend/ir/microinstruction.h @@ -109,7 +109,7 @@ public: /// Pseudo-instructions depend on their parent instructions for their semantics. bool IsAPseudoOperation() const; - /// Determins whether or not this instruction supports the GetNZCVFromOp pseudo-operation. + /// Determines whether or not this instruction supports the GetNZCVFromOp pseudo-operation. bool MayGetNZCVFromOp() const; /// Determines if all arguments of this instruction are immediates.