A32: Implement ASIMD VQRSHRUN

src/frontend/A32/decoder/asimd.inc

@@ -74,7 +74,7 @@ INST(asimd_VSLI,            "VSLI",                     "111100111Diiiiiidddd010
 INST(asimd_VSHRN,           "VSHRN",                    "111100101Diiiiiidddd100000M1mmmm") // ASIMD
 //INST(asimd_VRSHRN,          "VRSHRN",                   "111100101-vvv-------100001-1----") // ASIMD
 //INST(asimd_VQSHRUN,         "VQSHRUN",                  "111100111-vvv-------100000-1----") // ASIMD
-//INST(asimd_VQRSHRUN,        "VQRSHRUN",                 "111100111-vvv-------100001-1----") // ASIMD
+INST(asimd_VQRSHRUN,        "VQRSHRUN",                 "111100111Diiiiiidddd100001M1mmmm") // ASIMD
 //INST(asimd_VQSHRN,          "VQSHRN",                   "1111001U1-vvv-------100100-1----") // ASIMD
 //INST(asimd_VQRSHRN,         "VQRSHRN",                  "1111001U1-vvv-------100101-1----") // ASIMD
 //INST(asimd_SHLL,            "SHLL",                     "1111001U1-vvv-------101000-1----") // ASIMD

src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp

@@ -20,6 +20,17 @@ enum class Rounding {
     Round,
 };
 
+enum class Narrowing {
+    Truncation,
+    SaturateToUnsigned,
+    SaturateToSigned,
+};
+
+enum class Signedness {
+    Signed,
+    Unsigned
+};
+
 IR::U128 PerformRoundingCorrection(ArmTranslatorVisitor& v, size_t esize, u64 round_value, IR::U128 original, IR::U128 shifted) {
     const auto round_const = v.ir.VectorBroadcast(esize, v.I(esize, round_value));
     const auto round_correction = v.ir.VectorEqual(esize, v.ir.VectorAnd(original, round_const), round_const);
@@ -78,6 +89,57 @@ bool ShiftRight(ArmTranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd,
     v.ir.SetVector(d, result);
     return true;
 }
+
+bool ShiftRightNarrowing(ArmTranslatorVisitor& v, bool D, size_t imm6, size_t Vd, bool M, size_t Vm,
+                         Rounding rounding, Narrowing narrowing, Signedness signedness) {
+    if (Common::Bits<3, 5>(imm6) == 0) {
+        // TODO: Decode error
+        return v.UndefinedInstruction();
+    }
+
+    if (Common::Bit<0>(Vm)) {
+        return v.UndefinedInstruction();
+    }
+
+    const auto [esize, shift_amount_] = ElementSizeAndShiftAmount(true, false, imm6);
+    const auto source_esize = 2 * esize;
+    const auto shift_amount = static_cast<u8>(shift_amount_);
+
+    const auto d = ToVector(false, Vd, D);
+    const auto m = ToVector(true, Vm, M);
+
+    const auto reg_m = v.ir.GetVector(m);
+    auto wide_result = [&] {
+        if (signedness == Signedness::Signed) {
+            return v.ir.VectorArithmeticShiftRight(source_esize, reg_m, shift_amount);
+        }
+        return v.ir.VectorLogicalShiftRight(source_esize, reg_m, shift_amount);
+    }();
+
+    if (rounding == Rounding::Round) {
+        const u64 round_value = 1ULL << (shift_amount - 1);
+        wide_result = PerformRoundingCorrection(v, source_esize, round_value, reg_m, wide_result);
+    }
+
+    const auto result = [&] {
+        switch (narrowing) {
+        case Narrowing::Truncation:
+            return v.ir.VectorNarrow(source_esize, wide_result);
+        case Narrowing::SaturateToUnsigned:
+            if (signedness == Signedness::Signed) {
+                return v.ir.VectorSignedSaturatedNarrowToUnsigned(source_esize, wide_result);
+            }
+            return v.ir.VectorUnsignedSaturatedNarrow(source_esize, wide_result);
+        case Narrowing::SaturateToSigned:
+            ASSERT(signedness == Signedness::Signed);
+            return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
+        }
+        UNREACHABLE();
+    }();
+
+    v.ir.SetVector(d, result);
+    return true;
+}
 } // Anonymous namespace
 
 bool ArmTranslatorVisitor::asimd_SHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) {
@@ -176,25 +238,13 @@ bool ArmTranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bo
 }
 
 bool ArmTranslatorVisitor::asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) {
-    if (Common::Bits<3, 5>(imm6) == 0) {
+    return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm,
-        // TODO: Decode error
+                               Rounding::None, Narrowing::Truncation, Signedness::Unsigned);
-        return UndefinedInstruction();
+}
-    }
 
-    if (Common::Bit<0>(Vm)) {
+bool ArmTranslatorVisitor::asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) {
-        return UndefinedInstruction();
+    return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm,
-    }
+                               Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Signed);
-
-    const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, false, imm6);
-    const auto d = ToVector(false, Vd, D);
-    const auto m = ToVector(true, Vm, M);
-
-    const auto reg_m = ir.GetVector(m);
-    const auto wide_result = ir.VectorLogicalShiftRight(2 * esize, reg_m, shift_amount);
-    const auto result = ir.VectorNarrow(2 * esize, wide_result);
-
-    ir.SetVector(d, result);
-    return true;
 }
 
 } // namespace Dynarmic::A32

src/frontend/A32/translate/impl/translate_arm.h

@@ -509,6 +509,7 @@ struct ArmTranslatorVisitor final {
     bool asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
     bool asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
     bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
+    bool asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
 
     // Advanced SIMD two register, miscellaneous
     bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm);