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A32: Implement ASIMD VSHRN

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This commit is contained in:
MerryMage 2020-06-21 17:09:56 +01:00
parent 473949d486
commit e009d99924
3 changed files with 25 additions and 2 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -71,7 +71,7 @@ INST(asimd_VSRI, "VSRI", "111100111Diiiiiidddd010
INST(asimd_VSHL, "VSHL", "111100101Diiiiiidddd0101LQM1mmmm") // ASIMD
INST(asimd_VSLI, "VSLI", "111100111Diiiiiidddd0101LQM1mmmm") // ASIMD
//INST(asimd_VQSHL, "VQSHL" , "1111001U1-vvv-------011xLB-1----") // ASIMD
//INST(asimd_VSHRN, "VSHRN", "111100101-vvv-------100000-1----") // ASIMD
INST(asimd_VSHRN, "VSHRN", "111100101Diiiiiidddd100000M1mmmm") // ASIMD
//INST(asimd_VRSHRN, "VRSHRN", "111100101-vvv-------100001-1----") // ASIMD
//INST(asimd_VQSHRUN, "VQSHRUN", "111100111-vvv-------100000-1----") // ASIMD
//INST(asimd_VQRSHRUN, "VQRSHRUN", "111100111-vvv-------100001-1----") // ASIMD

22
src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
View file

@ -175,4 +175,26 @@ bool ArmTranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bo
return true;
}
bool ArmTranslatorVisitor::asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) {
if (Common::Bits<3, 5>(imm6) == 0) {
// TODO: Decode error
return UndefinedInstruction();
}
if (Common::Bit<0>(Vm)) {
return UndefinedInstruction();
}
const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, false, imm6);
const auto d = ToVector(false, Vd, D);
const auto m = ToVector(true, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto wide_result = ir.VectorLogicalShiftRight(2 * esize, reg_m, shift_amount);
const auto result = ir.VectorNarrow(2 * esize, wide_result);
ir.SetVector(d, result);
return true;
}
} // namespace Dynarmic::A32

3
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -506,8 +506,9 @@ struct ArmTranslatorVisitor final {
bool asimd_VRSHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSRI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
// Advanced SIMD two register, miscellaneous
bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm);