2018-12-20 23:09:21 +01:00
|
|
|
// Copyright 2018 yuzu Emulator Project
|
|
|
|
// Licensed under GPLv2 or any later version
|
|
|
|
// Refer to the license.txt file included.
|
|
|
|
|
2018-12-13 20:59:28 +01:00
|
|
|
#include <algorithm>
|
2018-12-21 05:27:47 +01:00
|
|
|
#include <vector>
|
2018-12-29 06:44:54 +01:00
|
|
|
#include <fmt/format.h>
|
2018-12-21 05:27:47 +01:00
|
|
|
|
2020-01-09 05:08:55 +01:00
|
|
|
#include "common/alignment.h"
|
2018-12-20 23:09:21 +01:00
|
|
|
#include "common/assert.h"
|
|
|
|
#include "common/common_types.h"
|
2019-04-02 04:03:32 +02:00
|
|
|
#include "common/logging/log.h"
|
2018-12-20 23:09:21 +01:00
|
|
|
#include "video_core/engines/shader_bytecode.h"
|
2019-06-05 03:44:06 +02:00
|
|
|
#include "video_core/shader/node_helper.h"
|
2018-12-20 23:09:21 +01:00
|
|
|
#include "video_core/shader/shader_ir.h"
|
|
|
|
|
|
|
|
namespace VideoCommon::Shader {
|
|
|
|
|
2020-01-16 08:00:52 +01:00
|
|
|
using Tegra::Shader::AtomicOp;
|
|
|
|
using Tegra::Shader::AtomicType;
|
2018-12-21 04:05:42 +01:00
|
|
|
using Tegra::Shader::Attribute;
|
2020-01-26 01:03:02 +01:00
|
|
|
using Tegra::Shader::GlobalAtomicType;
|
2018-12-20 23:09:21 +01:00
|
|
|
using Tegra::Shader::Instruction;
|
|
|
|
using Tegra::Shader::OpCode;
|
2018-12-21 04:05:42 +01:00
|
|
|
using Tegra::Shader::Register;
|
2020-01-25 07:15:55 +01:00
|
|
|
using Tegra::Shader::StoreType;
|
2018-12-20 23:09:21 +01:00
|
|
|
|
2019-02-07 04:05:41 +01:00
|
|
|
namespace {
|
2019-11-01 04:34:38 +01:00
|
|
|
|
2020-03-31 03:02:44 +02:00
|
|
|
Node GetAtomOperation(AtomicOp op, bool is_signed, Node memory, Node data) {
|
|
|
|
const OperationCode operation_code = [op] {
|
|
|
|
switch (op) {
|
|
|
|
case AtomicOp::Add:
|
|
|
|
return OperationCode::AtomicIAdd;
|
|
|
|
case AtomicOp::Min:
|
|
|
|
return OperationCode::AtomicIMin;
|
|
|
|
case AtomicOp::Max:
|
|
|
|
return OperationCode::AtomicIMax;
|
|
|
|
case AtomicOp::And:
|
|
|
|
return OperationCode::AtomicIAnd;
|
|
|
|
case AtomicOp::Or:
|
|
|
|
return OperationCode::AtomicIOr;
|
|
|
|
case AtomicOp::Xor:
|
|
|
|
return OperationCode::AtomicIXor;
|
|
|
|
case AtomicOp::Exch:
|
|
|
|
return OperationCode::AtomicIExchange;
|
|
|
|
}
|
|
|
|
}();
|
|
|
|
return SignedOperation(operation_code, is_signed, std::move(memory),
|
2020-03-30 13:47:50 +02:00
|
|
|
std::move(data));
|
|
|
|
}
|
|
|
|
|
2020-01-09 05:08:55 +01:00
|
|
|
bool IsUnaligned(Tegra::Shader::UniformType uniform_type) {
|
|
|
|
return uniform_type == Tegra::Shader::UniformType::UnsignedByte ||
|
|
|
|
uniform_type == Tegra::Shader::UniformType::UnsignedShort;
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 GetUnalignedMask(Tegra::Shader::UniformType uniform_type) {
|
2019-12-18 04:36:21 +01:00
|
|
|
switch (uniform_type) {
|
|
|
|
case Tegra::Shader::UniformType::UnsignedByte:
|
2020-01-09 05:08:55 +01:00
|
|
|
return 0b11;
|
|
|
|
case Tegra::Shader::UniformType::UnsignedShort:
|
|
|
|
return 0b10;
|
2019-12-18 04:36:21 +01:00
|
|
|
default:
|
2020-01-09 05:08:55 +01:00
|
|
|
UNREACHABLE();
|
|
|
|
return 0;
|
2019-12-18 04:36:21 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-01-09 05:08:55 +01:00
|
|
|
u32 GetMemorySize(Tegra::Shader::UniformType uniform_type) {
|
2019-02-07 04:05:41 +01:00
|
|
|
switch (uniform_type) {
|
2020-01-09 05:08:55 +01:00
|
|
|
case Tegra::Shader::UniformType::UnsignedByte:
|
|
|
|
return 8;
|
|
|
|
case Tegra::Shader::UniformType::UnsignedShort:
|
|
|
|
return 16;
|
2019-02-07 04:05:41 +01:00
|
|
|
case Tegra::Shader::UniformType::Single:
|
2020-01-09 05:08:55 +01:00
|
|
|
return 32;
|
2019-02-07 04:05:41 +01:00
|
|
|
case Tegra::Shader::UniformType::Double:
|
2020-01-09 05:08:55 +01:00
|
|
|
return 64;
|
2019-02-07 04:05:41 +01:00
|
|
|
case Tegra::Shader::UniformType::Quad:
|
|
|
|
case Tegra::Shader::UniformType::UnsignedQuad:
|
2020-01-09 05:08:55 +01:00
|
|
|
return 128;
|
2019-02-07 04:05:41 +01:00
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("Unimplemented size={}!", static_cast<u32>(uniform_type));
|
2020-01-09 05:08:55 +01:00
|
|
|
return 32;
|
2019-02-07 04:05:41 +01:00
|
|
|
}
|
|
|
|
}
|
2019-11-01 04:34:38 +01:00
|
|
|
|
2020-01-25 06:18:14 +01:00
|
|
|
Node ExtractUnaligned(Node value, Node address, u32 mask, u32 size) {
|
|
|
|
Node offset = Operation(OperationCode::UBitwiseAnd, address, Immediate(mask));
|
|
|
|
offset = Operation(OperationCode::ULogicalShiftLeft, std::move(offset), Immediate(3));
|
|
|
|
return Operation(OperationCode::UBitfieldExtract, std::move(value), std::move(offset),
|
|
|
|
Immediate(size));
|
|
|
|
}
|
|
|
|
|
|
|
|
Node InsertUnaligned(Node dest, Node value, Node address, u32 mask, u32 size) {
|
|
|
|
Node offset = Operation(OperationCode::UBitwiseAnd, std::move(address), Immediate(mask));
|
|
|
|
offset = Operation(OperationCode::ULogicalShiftLeft, std::move(offset), Immediate(3));
|
|
|
|
return Operation(OperationCode::UBitfieldInsert, std::move(dest), std::move(value),
|
|
|
|
std::move(offset), Immediate(size));
|
|
|
|
}
|
|
|
|
|
2020-01-25 07:15:55 +01:00
|
|
|
Node Sign16Extend(Node value) {
|
|
|
|
Node sign = Operation(OperationCode::UBitwiseAnd, value, Immediate(1U << 15));
|
|
|
|
Node is_sign = Operation(OperationCode::LogicalUEqual, std::move(sign), Immediate(1U << 15));
|
|
|
|
Node extend = Operation(OperationCode::Select, is_sign, Immediate(0xFFFF0000), Immediate(0));
|
|
|
|
return Operation(OperationCode::UBitwiseOr, std::move(value), std::move(extend));
|
|
|
|
}
|
|
|
|
|
2019-07-30 05:21:46 +02:00
|
|
|
} // Anonymous namespace
|
2019-02-07 04:05:41 +01:00
|
|
|
|
2019-01-30 06:09:40 +01:00
|
|
|
u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
|
2018-12-20 23:09:21 +01:00
|
|
|
const Instruction instr = {program_code[pc]};
|
|
|
|
const auto opcode = OpCode::Decode(instr);
|
|
|
|
|
2018-12-21 04:05:42 +01:00
|
|
|
switch (opcode->get().GetId()) {
|
|
|
|
case OpCode::Id::LD_A: {
|
|
|
|
// Note: Shouldn't this be interp mode flat? As in no interpolation made.
|
|
|
|
UNIMPLEMENTED_IF_MSG(instr.gpr8.Value() != Register::ZeroIndex,
|
|
|
|
"Indirect attribute loads are not supported");
|
|
|
|
UNIMPLEMENTED_IF_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) != 0,
|
|
|
|
"Unaligned attribute loads are not supported");
|
2019-05-01 01:11:41 +02:00
|
|
|
UNIMPLEMENTED_IF_MSG(instr.attribute.fmt20.IsPhysical() &&
|
|
|
|
instr.attribute.fmt20.size != Tegra::Shader::AttributeSize::Word,
|
|
|
|
"Non-32 bits PHYS reads are not implemented");
|
2018-12-21 04:05:42 +01:00
|
|
|
|
2019-04-30 23:12:30 +02:00
|
|
|
const Node buffer{GetRegister(instr.gpr39)};
|
|
|
|
|
2018-12-21 04:05:42 +01:00
|
|
|
u64 next_element = instr.attribute.fmt20.element;
|
|
|
|
auto next_index = static_cast<u64>(instr.attribute.fmt20.index.Value());
|
|
|
|
|
|
|
|
const auto LoadNextElement = [&](u32 reg_offset) {
|
2019-04-30 23:12:30 +02:00
|
|
|
const Node attribute{instr.attribute.fmt20.IsPhysical()
|
|
|
|
? GetPhysicalInputAttribute(instr.gpr8, buffer)
|
|
|
|
: GetInputAttribute(static_cast<Attribute::Index>(next_index),
|
|
|
|
next_element, buffer)};
|
2018-12-21 04:05:42 +01:00
|
|
|
|
|
|
|
SetRegister(bb, instr.gpr0.Value() + reg_offset, attribute);
|
|
|
|
|
|
|
|
// Load the next attribute element into the following register. If the element
|
|
|
|
// to load goes beyond the vec4 size, load the first element of the next
|
|
|
|
// attribute.
|
|
|
|
next_element = (next_element + 1) % 4;
|
|
|
|
next_index = next_index + (next_element == 0 ? 1 : 0);
|
|
|
|
};
|
|
|
|
|
|
|
|
const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
|
|
|
|
for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
|
|
|
|
LoadNextElement(reg_offset);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2018-12-21 06:08:52 +01:00
|
|
|
case OpCode::Id::LD_C: {
|
|
|
|
UNIMPLEMENTED_IF(instr.ld_c.unknown != 0);
|
|
|
|
|
|
|
|
Node index = GetRegister(instr.gpr8);
|
|
|
|
|
|
|
|
const Node op_a =
|
2019-01-28 22:11:23 +01:00
|
|
|
GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 0, index);
|
2018-12-21 06:08:52 +01:00
|
|
|
|
|
|
|
switch (instr.ld_c.type.Value()) {
|
|
|
|
case Tegra::Shader::UniformType::Single:
|
|
|
|
SetRegister(bb, instr.gpr0, op_a);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case Tegra::Shader::UniformType::Double: {
|
|
|
|
const Node op_b =
|
2019-01-28 22:11:23 +01:00
|
|
|
GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 4, index);
|
2018-12-21 06:08:52 +01:00
|
|
|
|
2019-07-16 16:31:17 +02:00
|
|
|
SetTemporary(bb, 0, op_a);
|
|
|
|
SetTemporary(bb, 1, op_b);
|
|
|
|
SetRegister(bb, instr.gpr0, GetTemporary(0));
|
|
|
|
SetRegister(bb, instr.gpr0.Value() + 1, GetTemporary(1));
|
2018-12-21 06:08:52 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("Unhandled type: {}", static_cast<unsigned>(instr.ld_c.type.Value()));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2019-08-09 20:35:28 +02:00
|
|
|
case OpCode::Id::LD_L:
|
|
|
|
LOG_DEBUG(HW_GPU, "LD_L cache management mode: {}", static_cast<u64>(instr.ld_l.unknown));
|
|
|
|
[[fallthrough]];
|
|
|
|
case OpCode::Id::LD_S: {
|
2020-01-25 06:18:14 +01:00
|
|
|
const auto GetAddress = [&](s32 offset) {
|
2019-02-03 03:43:11 +01:00
|
|
|
ASSERT(offset % 4 == 0);
|
|
|
|
const Node immediate_offset = Immediate(static_cast<s32>(instr.smem_imm) + offset);
|
2020-01-25 06:18:14 +01:00
|
|
|
return Operation(OperationCode::IAdd, GetRegister(instr.gpr8), immediate_offset);
|
|
|
|
};
|
|
|
|
const auto GetMemory = [&](s32 offset) {
|
|
|
|
return opcode->get().GetId() == OpCode::Id::LD_S ? GetSharedMemory(GetAddress(offset))
|
|
|
|
: GetLocalMemory(GetAddress(offset));
|
2019-02-03 03:43:11 +01:00
|
|
|
};
|
2018-12-21 06:33:15 +01:00
|
|
|
|
|
|
|
switch (instr.ldst_sl.type.Value()) {
|
2020-01-25 06:21:05 +01:00
|
|
|
case StoreType::Signed16:
|
|
|
|
SetRegister(bb, instr.gpr0,
|
|
|
|
Sign16Extend(ExtractUnaligned(GetMemory(0), GetAddress(0), 0b10, 16)));
|
2020-01-25 07:15:55 +01:00
|
|
|
break;
|
|
|
|
case StoreType::Bits32:
|
|
|
|
case StoreType::Bits64:
|
|
|
|
case StoreType::Bits128: {
|
|
|
|
const u32 count = [&] {
|
2019-02-03 04:35:20 +01:00
|
|
|
switch (instr.ldst_sl.type.Value()) {
|
2020-01-25 07:15:55 +01:00
|
|
|
case StoreType::Bits32:
|
2019-02-03 04:35:20 +01:00
|
|
|
return 1;
|
2020-01-25 07:15:55 +01:00
|
|
|
case StoreType::Bits64:
|
2019-02-03 04:35:20 +01:00
|
|
|
return 2;
|
2020-01-25 07:15:55 +01:00
|
|
|
case StoreType::Bits128:
|
2019-02-03 04:35:20 +01:00
|
|
|
return 4;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}();
|
2019-08-09 20:35:28 +02:00
|
|
|
for (u32 i = 0; i < count; ++i) {
|
|
|
|
SetTemporary(bb, i, GetMemory(i * 4));
|
|
|
|
}
|
|
|
|
for (u32 i = 0; i < count; ++i) {
|
2019-07-16 16:31:17 +02:00
|
|
|
SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
|
2019-08-09 20:35:28 +02:00
|
|
|
}
|
2018-12-21 06:33:15 +01:00
|
|
|
break;
|
2019-02-03 03:43:11 +01:00
|
|
|
}
|
2018-12-21 06:33:15 +01:00
|
|
|
default:
|
2019-08-09 20:35:28 +02:00
|
|
|
UNIMPLEMENTED_MSG("{} Unhandled type: {}", opcode->get().GetName(),
|
2019-02-03 03:44:38 +01:00
|
|
|
static_cast<u32>(instr.ldst_sl.type.Value()));
|
2018-12-21 06:33:15 +01:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2019-05-18 07:35:01 +02:00
|
|
|
case OpCode::Id::LD:
|
2018-12-29 06:44:54 +01:00
|
|
|
case OpCode::Id::LDG: {
|
2019-05-18 07:35:01 +02:00
|
|
|
const auto type = [instr, &opcode]() -> Tegra::Shader::UniformType {
|
|
|
|
switch (opcode->get().GetId()) {
|
|
|
|
case OpCode::Id::LD:
|
|
|
|
UNIMPLEMENTED_IF_MSG(!instr.generic.extended, "Unextended LD is not implemented");
|
|
|
|
return instr.generic.type;
|
|
|
|
case OpCode::Id::LDG:
|
|
|
|
return instr.ldg.type;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
return {};
|
|
|
|
}
|
|
|
|
}();
|
|
|
|
|
2019-02-07 04:05:41 +01:00
|
|
|
const auto [real_address_base, base_address, descriptor] =
|
2020-01-09 05:08:55 +01:00
|
|
|
TrackGlobalMemory(bb, instr, true, false);
|
2018-12-29 06:44:54 +01:00
|
|
|
|
2020-01-09 05:08:55 +01:00
|
|
|
const u32 size = GetMemorySize(type);
|
|
|
|
const u32 count = Common::AlignUp(size, 32) / 32;
|
2019-10-18 06:23:10 +02:00
|
|
|
if (!real_address_base || !base_address) {
|
|
|
|
// Tracking failed, load zeroes.
|
|
|
|
for (u32 i = 0; i < count; ++i) {
|
|
|
|
SetRegister(bb, instr.gpr0.Value() + i, Immediate(0.0f));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-12-29 06:44:54 +01:00
|
|
|
for (u32 i = 0; i < count; ++i) {
|
|
|
|
const Node it_offset = Immediate(i * 4);
|
2019-12-18 04:36:21 +01:00
|
|
|
const Node real_address = Operation(OperationCode::UAdd, real_address_base, it_offset);
|
|
|
|
Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
|
|
|
|
|
2020-01-09 05:08:55 +01:00
|
|
|
// To handle unaligned loads get the bytes used to dereference global memory and extract
|
|
|
|
// those bytes from the loaded u32.
|
|
|
|
if (IsUnaligned(type)) {
|
2020-01-25 06:18:14 +01:00
|
|
|
gmem = ExtractUnaligned(gmem, real_address, GetUnalignedMask(type), size);
|
2019-12-18 04:36:21 +01:00
|
|
|
}
|
2018-12-29 06:44:54 +01:00
|
|
|
|
2019-07-16 16:31:17 +02:00
|
|
|
SetTemporary(bb, i, gmem);
|
2018-12-29 06:44:54 +01:00
|
|
|
}
|
2019-12-18 04:36:21 +01:00
|
|
|
|
2018-12-29 06:44:54 +01:00
|
|
|
for (u32 i = 0; i < count; ++i) {
|
2019-07-16 16:31:17 +02:00
|
|
|
SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
|
2018-12-29 06:44:54 +01:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2018-12-21 04:06:13 +01:00
|
|
|
case OpCode::Id::ST_A: {
|
|
|
|
UNIMPLEMENTED_IF_MSG(instr.gpr8.Value() != Register::ZeroIndex,
|
|
|
|
"Indirect attribute loads are not supported");
|
|
|
|
UNIMPLEMENTED_IF_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) != 0,
|
|
|
|
"Unaligned attribute loads are not supported");
|
|
|
|
|
2019-11-01 04:34:38 +01:00
|
|
|
u64 element = instr.attribute.fmt20.element;
|
|
|
|
auto index = static_cast<u64>(instr.attribute.fmt20.index.Value());
|
2018-12-21 04:06:13 +01:00
|
|
|
|
2019-11-01 04:34:38 +01:00
|
|
|
const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
|
|
|
|
for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
|
|
|
|
Node dest;
|
|
|
|
if (instr.attribute.fmt20.patch) {
|
|
|
|
const u32 offset = static_cast<u32>(index) * 4 + static_cast<u32>(element);
|
|
|
|
dest = MakeNode<PatchNode>(offset);
|
|
|
|
} else {
|
|
|
|
dest = GetOutputAttribute(static_cast<Attribute::Index>(index), element,
|
|
|
|
GetRegister(instr.gpr39));
|
|
|
|
}
|
2018-12-21 04:06:13 +01:00
|
|
|
const auto src = GetRegister(instr.gpr0.Value() + reg_offset);
|
|
|
|
|
|
|
|
bb.push_back(Operation(OperationCode::Assign, dest, src));
|
|
|
|
|
2019-11-01 04:34:38 +01:00
|
|
|
// Load the next attribute element into the following register. If the element to load
|
|
|
|
// goes beyond the vec4 size, load the first element of the next attribute.
|
|
|
|
element = (element + 1) % 4;
|
|
|
|
index = index + (element == 0 ? 1 : 0);
|
2018-12-21 04:06:13 +01:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2019-07-30 05:21:46 +02:00
|
|
|
case OpCode::Id::ST_L:
|
2019-04-02 04:03:32 +02:00
|
|
|
LOG_DEBUG(HW_GPU, "ST_L cache management mode: {}",
|
|
|
|
static_cast<u64>(instr.st_l.cache_management.Value()));
|
2019-07-30 05:21:46 +02:00
|
|
|
[[fallthrough]];
|
|
|
|
case OpCode::Id::ST_S: {
|
|
|
|
const auto GetAddress = [&](s32 offset) {
|
2019-02-03 23:08:10 +01:00
|
|
|
ASSERT(offset % 4 == 0);
|
|
|
|
const Node immediate = Immediate(static_cast<s32>(instr.smem_imm) + offset);
|
|
|
|
return Operation(OperationCode::IAdd, NO_PRECISE, GetRegister(instr.gpr8), immediate);
|
|
|
|
};
|
2018-12-21 06:33:31 +01:00
|
|
|
|
2020-01-25 06:30:20 +01:00
|
|
|
const bool is_local = opcode->get().GetId() == OpCode::Id::ST_L;
|
|
|
|
const auto set_memory = is_local ? &ShaderIR::SetLocalMemory : &ShaderIR::SetSharedMemory;
|
|
|
|
const auto get_memory = is_local ? &ShaderIR::GetLocalMemory : &ShaderIR::GetSharedMemory;
|
2019-07-30 05:21:46 +02:00
|
|
|
|
2018-12-21 06:33:31 +01:00
|
|
|
switch (instr.ldst_sl.type.Value()) {
|
2020-01-25 07:15:55 +01:00
|
|
|
case StoreType::Bits128:
|
2019-07-30 05:21:46 +02:00
|
|
|
(this->*set_memory)(bb, GetAddress(12), GetRegister(instr.gpr0.Value() + 3));
|
|
|
|
(this->*set_memory)(bb, GetAddress(8), GetRegister(instr.gpr0.Value() + 2));
|
|
|
|
[[fallthrough]];
|
2020-01-25 07:15:55 +01:00
|
|
|
case StoreType::Bits64:
|
2019-07-30 05:21:46 +02:00
|
|
|
(this->*set_memory)(bb, GetAddress(4), GetRegister(instr.gpr0.Value() + 1));
|
|
|
|
[[fallthrough]];
|
2020-01-25 07:15:55 +01:00
|
|
|
case StoreType::Bits32:
|
2019-07-30 05:21:46 +02:00
|
|
|
(this->*set_memory)(bb, GetAddress(0), GetRegister(instr.gpr0));
|
2018-12-21 06:33:31 +01:00
|
|
|
break;
|
2020-01-25 06:30:20 +01:00
|
|
|
case StoreType::Signed16: {
|
|
|
|
Node address = GetAddress(0);
|
|
|
|
Node memory = (this->*get_memory)(address);
|
|
|
|
(this->*set_memory)(
|
|
|
|
bb, address, InsertUnaligned(memory, GetRegister(instr.gpr0), address, 0b10, 16));
|
|
|
|
break;
|
|
|
|
}
|
2018-12-21 06:33:31 +01:00
|
|
|
default:
|
2019-07-30 05:21:46 +02:00
|
|
|
UNIMPLEMENTED_MSG("{} unhandled type: {}", opcode->get().GetName(),
|
2018-12-21 06:33:31 +01:00
|
|
|
static_cast<u32>(instr.ldst_sl.type.Value()));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2019-05-18 07:51:12 +02:00
|
|
|
case OpCode::Id::ST:
|
|
|
|
case OpCode::Id::STG: {
|
|
|
|
const auto type = [instr, &opcode]() -> Tegra::Shader::UniformType {
|
|
|
|
switch (opcode->get().GetId()) {
|
|
|
|
case OpCode::Id::ST:
|
|
|
|
UNIMPLEMENTED_IF_MSG(!instr.generic.extended, "Unextended ST is not implemented");
|
|
|
|
return instr.generic.type;
|
|
|
|
case OpCode::Id::STG:
|
|
|
|
return instr.stg.type;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
return {};
|
|
|
|
}
|
|
|
|
}();
|
|
|
|
|
2020-01-09 05:08:55 +01:00
|
|
|
// For unaligned reads we have to read memory too.
|
|
|
|
const bool is_read = IsUnaligned(type);
|
2019-05-18 07:51:12 +02:00
|
|
|
const auto [real_address_base, base_address, descriptor] =
|
2020-01-09 05:08:55 +01:00
|
|
|
TrackGlobalMemory(bb, instr, is_read, true);
|
2019-10-18 06:23:10 +02:00
|
|
|
if (!real_address_base || !base_address) {
|
|
|
|
// Tracking failed, skip the store.
|
|
|
|
break;
|
|
|
|
}
|
2019-05-18 07:51:12 +02:00
|
|
|
|
2020-01-09 05:08:55 +01:00
|
|
|
const u32 size = GetMemorySize(type);
|
|
|
|
const u32 count = Common::AlignUp(size, 32) / 32;
|
2019-05-18 07:51:12 +02:00
|
|
|
for (u32 i = 0; i < count; ++i) {
|
|
|
|
const Node it_offset = Immediate(i * 4);
|
2019-10-18 06:23:10 +02:00
|
|
|
const Node real_address = Operation(OperationCode::UAdd, real_address_base, it_offset);
|
2019-06-05 03:44:06 +02:00
|
|
|
const Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
|
2020-01-09 05:08:55 +01:00
|
|
|
Node value = GetRegister(instr.gpr0.Value() + i);
|
|
|
|
|
|
|
|
if (IsUnaligned(type)) {
|
2020-01-25 06:18:14 +01:00
|
|
|
const u32 mask = GetUnalignedMask(type);
|
|
|
|
value = InsertUnaligned(gmem, std::move(value), real_address, mask, size);
|
2020-01-09 05:08:55 +01:00
|
|
|
}
|
|
|
|
|
2019-10-18 06:23:10 +02:00
|
|
|
bb.push_back(Operation(OperationCode::Assign, gmem, value));
|
2019-05-18 07:51:12 +02:00
|
|
|
}
|
|
|
|
break;
|
2020-01-16 08:00:52 +01:00
|
|
|
}
|
2020-01-26 01:03:02 +01:00
|
|
|
case OpCode::Id::ATOM: {
|
2020-03-30 13:47:50 +02:00
|
|
|
UNIMPLEMENTED_IF_MSG(instr.atom.operation == AtomicOp::Inc ||
|
|
|
|
instr.atom.operation == AtomicOp::Dec ||
|
|
|
|
instr.atom.operation == AtomicOp::SafeAdd,
|
2020-03-13 19:23:47 +01:00
|
|
|
"operation={}", static_cast<int>(instr.atom.operation.Value()));
|
|
|
|
UNIMPLEMENTED_IF_MSG(instr.atom.type == GlobalAtomicType::S64 ||
|
|
|
|
instr.atom.type == GlobalAtomicType::U64,
|
|
|
|
"type={}", static_cast<int>(instr.atom.type.Value()));
|
2020-01-26 01:03:02 +01:00
|
|
|
|
|
|
|
const auto [real_address, base_address, descriptor] =
|
|
|
|
TrackGlobalMemory(bb, instr, true, true);
|
|
|
|
if (!real_address || !base_address) {
|
|
|
|
// Tracking failed, skip atomic.
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-03-13 19:23:47 +01:00
|
|
|
const bool is_signed =
|
|
|
|
instr.atoms.type == AtomicType::S32 || instr.atoms.type == AtomicType::S64;
|
2020-01-26 01:03:02 +01:00
|
|
|
Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
|
2020-03-31 03:02:44 +02:00
|
|
|
Node value = GetAtomOperation(static_cast<AtomicOp>(instr.atom.operation), is_signed, gmem,
|
2020-03-30 13:47:50 +02:00
|
|
|
GetRegister(instr.gpr20));
|
2020-01-26 01:03:02 +01:00
|
|
|
SetRegister(bb, instr.gpr0, std::move(value));
|
|
|
|
break;
|
|
|
|
}
|
2020-01-16 08:00:52 +01:00
|
|
|
case OpCode::Id::ATOMS: {
|
2020-03-13 17:09:41 +01:00
|
|
|
UNIMPLEMENTED_IF_MSG(instr.atoms.operation == AtomicOp::Inc ||
|
|
|
|
instr.atoms.operation == AtomicOp::Dec,
|
|
|
|
"operation={}", static_cast<int>(instr.atoms.operation.Value()));
|
|
|
|
UNIMPLEMENTED_IF_MSG(instr.atoms.type == AtomicType::S64 ||
|
|
|
|
instr.atoms.type == AtomicType::U64,
|
|
|
|
"type={}", static_cast<int>(instr.atoms.type.Value()));
|
|
|
|
const bool is_signed =
|
|
|
|
instr.atoms.type == AtomicType::S32 || instr.atoms.type == AtomicType::S64;
|
2020-01-16 08:00:52 +01:00
|
|
|
const s32 offset = instr.atoms.GetImmediateOffset();
|
|
|
|
Node address = GetRegister(instr.gpr8);
|
|
|
|
address = Operation(OperationCode::IAdd, std::move(address), Immediate(offset));
|
2020-03-30 13:47:50 +02:00
|
|
|
Node value =
|
2020-03-31 03:02:44 +02:00
|
|
|
GetAtomOperation(static_cast<AtomicOp>(instr.atoms.operation), is_signed,
|
2020-03-30 13:47:50 +02:00
|
|
|
GetSharedMemory(std::move(address)), GetRegister(instr.gpr20));
|
2020-01-16 08:00:52 +01:00
|
|
|
SetRegister(bb, instr.gpr0, std::move(value));
|
|
|
|
break;
|
2019-05-18 07:51:12 +02:00
|
|
|
}
|
2019-04-30 04:28:28 +02:00
|
|
|
case OpCode::Id::AL2P: {
|
|
|
|
// Ignore al2p.direction since we don't care about it.
|
|
|
|
|
|
|
|
// Calculate emulation fake physical address.
|
|
|
|
const Node fixed_address{Immediate(static_cast<u32>(instr.al2p.address))};
|
|
|
|
const Node reg{GetRegister(instr.gpr8)};
|
|
|
|
const Node fake_address{Operation(OperationCode::IAdd, NO_PRECISE, reg, fixed_address)};
|
|
|
|
|
|
|
|
// Set the fake address to target register.
|
|
|
|
SetRegister(bb, instr.gpr0, fake_address);
|
|
|
|
|
|
|
|
// Signal the shader IR to declare all possible attributes and varyings
|
2019-05-01 00:46:49 +02:00
|
|
|
uses_physical_attributes = true;
|
2019-04-30 04:28:28 +02:00
|
|
|
break;
|
|
|
|
}
|
2018-12-21 04:05:42 +01:00
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("Unhandled memory instruction: {}", opcode->get().GetName());
|
|
|
|
}
|
2018-12-20 23:09:21 +01:00
|
|
|
|
|
|
|
return pc;
|
|
|
|
}
|
|
|
|
|
2019-10-18 06:23:10 +02:00
|
|
|
std::tuple<Node, Node, GlobalMemoryBase> ShaderIR::TrackGlobalMemory(NodeBlock& bb,
|
|
|
|
Instruction instr,
|
2020-01-09 05:08:55 +01:00
|
|
|
bool is_read, bool is_write) {
|
2019-05-18 07:35:01 +02:00
|
|
|
const auto addr_register{GetRegister(instr.gmem.gpr)};
|
|
|
|
const auto immediate_offset{static_cast<u32>(instr.gmem.offset)};
|
|
|
|
|
2019-06-01 00:14:34 +02:00
|
|
|
const auto [base_address, index, offset] =
|
|
|
|
TrackCbuf(addr_register, global_code, static_cast<s64>(global_code.size()));
|
2020-03-30 15:46:21 +02:00
|
|
|
ASSERT_OR_EXECUTE_MSG(base_address != nullptr,
|
|
|
|
{ return std::make_tuple(nullptr, nullptr, GlobalMemoryBase{}); },
|
|
|
|
"Global memory tracking failed");
|
2019-06-01 00:14:34 +02:00
|
|
|
|
|
|
|
bb.push_back(Comment(fmt::format("Base address is c[0x{:x}][0x{:x}]", index, offset)));
|
|
|
|
|
|
|
|
const GlobalMemoryBase descriptor{index, offset};
|
2019-02-07 04:05:41 +01:00
|
|
|
const auto& [entry, is_new] = used_global_memory.try_emplace(descriptor);
|
|
|
|
auto& usage = entry->second;
|
2020-01-09 05:08:55 +01:00
|
|
|
usage.is_written |= is_write;
|
|
|
|
usage.is_read |= is_read;
|
2019-02-07 04:05:41 +01:00
|
|
|
|
|
|
|
const auto real_address =
|
|
|
|
Operation(OperationCode::UAdd, NO_PRECISE, Immediate(immediate_offset), addr_register);
|
|
|
|
|
|
|
|
return {real_address, base_address, descriptor};
|
|
|
|
}
|
|
|
|
|
2019-02-03 22:07:20 +01:00
|
|
|
} // namespace VideoCommon::Shader
|