Suppport AESCE on A32 and T32
Signed-off-by: Dave Rodgman <dave.rodgman@arm.com>
This commit is contained in:
Dave Rodgman
parent
d69d3cda34
commit
27e3c87fc1
3 changed files with 84 additions and 8 deletions
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@ -35,9 +35,9 @@
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#include "mbedtls/error.h"
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#if defined(MBEDTLS_AES_USE_HARDWARE_ONLY)
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#if !((defined(MBEDTLS_ARCH_IS_ARM64) && defined(MBEDTLS_AESCE_C)) || \
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(defined(MBEDTLS_ARCH_IS_X64) && defined(MBEDTLS_AESNI_C)) || \
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(defined(MBEDTLS_ARCH_IS_X86) && defined(MBEDTLS_AESNI_C)))
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#if !((defined(MBEDTLS_ARCH_IS_ARMV8) && defined(MBEDTLS_AESCE_C)) || \
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(defined(MBEDTLS_ARCH_IS_X64) && defined(MBEDTLS_AESNI_C)) || \
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(defined(MBEDTLS_ARCH_IS_X86) && defined(MBEDTLS_AESNI_C)))
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#error "MBEDTLS_AES_USE_HARDWARE_ONLY defined, but not all prerequisites"
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#endif
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#endif
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@ -17,8 +17,17 @@
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* limitations under the License.
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*/
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#if defined(__aarch64__) && !defined(__ARM_FEATURE_CRYPTO) && \
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defined(__clang__) && __clang_major__ >= 4
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#if defined(__clang__) && (__clang_major__ >= 4)
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/* Ideally, we would simply use MBEDTLS_ARCH_IS_ARMV8 in the following #if,
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* but that is defined by build_info.h, and we need this block to happen first. */
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#if defined(__ARM_ARCH)
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#if __ARM_ARCH >= 8
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#define MBEDTLS_AESCE_ARCH_IS_ARMV8
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#endif
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#endif
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#if defined(MBEDTLS_AESCE_ARCH_IS_ARMV8) && !defined(__ARM_FEATURE_CRYPTO)
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/* TODO: Re-consider above after https://reviews.llvm.org/D131064 merged.
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*
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* The intrinsic declaration are guarded by predefined ACLE macros in clang:
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@ -39,6 +48,8 @@
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#define MBEDTLS_ENABLE_ARM_CRYPTO_EXTENSIONS_COMPILER_FLAG
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#endif
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#endif /* defined(__clang__) && (__clang_major__ >= 4) */
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#include <string.h>
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#include "common.h"
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@ -46,7 +57,7 @@
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#include "aesce.h"
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#if defined(MBEDTLS_ARCH_IS_ARM64)
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#if defined(MBEDTLS_ARCH_IS_ARMV8)
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/* Compiler version checks. */
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#if defined(__clang__)
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@ -68,6 +79,71 @@
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#ifdef __ARM_NEON
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#include <arm_neon.h>
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#if defined(MBEDTLS_ARCH_IS_ARM32)
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#if defined(__clang__)
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/* On clang for A32/T32, work around some missing intrinsics and types */
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#ifndef vreinterpretq_p64_u8
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#define vreinterpretq_p64_u8 (poly64x2_t)
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#endif
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#ifndef vreinterpretq_u8_p128
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#define vreinterpretq_u8_p128 (uint8x16_t)
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#endif
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#ifndef vreinterpretq_u64_p64
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#define vreinterpretq_u64_p64 (uint64x2_t)
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#endif
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typedef uint8x16_t poly128_t;
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static inline poly128_t vmull_p64(poly64_t a, poly64_t b)
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{
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poly128_t r;
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asm ("vmull.p64 %[r], %[a], %[b]": [r] "=w" (r) : [a] "w" (a), [b] "w" (b) :);
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return r;
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}
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static inline poly64x1_t vget_low_p64(poly64x2_t a)
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{
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return (poly64x1_t) vget_low_u64(vreinterpretq_u64_p64(a));
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}
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static inline poly128_t vmull_high_p64(poly64x2_t a, poly64x2_t b)
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{
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return vmull_p64((poly64_t) (vget_high_u64((uint64x2_t) a)),
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(poly64_t) (vget_high_u64((uint64x2_t) b)));
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}
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#endif /* defined(__clang__) */
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static inline uint8x16_t vrbitq_u8(uint8x16_t x)
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{
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/* There is no vrbitq_u8 instruction in A32/T32, so provide
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* an equivalent non-Neon implementation. Reverse bit order in each
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* byte with 4x rbit, rev. */
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asm ("ldm %[p], { r2-r5 } \n\t"
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"rbit r2, r2 \n\t"
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"rev r2, r2 \n\t"
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"rbit r3, r3 \n\t"
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"rev r3, r3 \n\t"
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"rbit r4, r4 \n\t"
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"rev r4, r4 \n\t"
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"rbit r5, r5 \n\t"
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"rev r5, r5 \n\t"
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"stm %[p], { r2-r5 } \n\t"
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:
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/* Output: 16 bytes of memory pointed to by &x */
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"+m" (*(uint8_t(*)[16]) &x)
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:
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[p] "r" (&x)
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:
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"r2", "r3", "r4", "r5"
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);
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return x;
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}
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#endif /* defined(MBEDTLS_ARCH_IS_ARM32) */
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#else
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#error "Target does not support NEON instructions"
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#endif
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@ -510,6 +586,6 @@ void mbedtls_aesce_gcm_mult(unsigned char c[16],
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#undef MBEDTLS_POP_TARGET_PRAGMA
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#endif
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#endif /* MBEDTLS_ARCH_IS_ARM64 */
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#endif /* MBEDTLS_ARCH_IS_ARMV8 */
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#endif /* MBEDTLS_AESCE_C */
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@ -31,7 +31,7 @@
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#include "mbedtls/aes.h"
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#if defined(MBEDTLS_AESCE_C) && defined(MBEDTLS_ARCH_IS_ARM64)
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#if defined(MBEDTLS_AESCE_C) && defined(MBEDTLS_ARCH_IS_ARMV8)
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#define MBEDTLS_AESCE_HAVE_CODE
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