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108 commits

Author SHA1 Message Date
MerryMage
8a5356357f externals: Update dynarmic to 3806284cb 2021-01-02 20:42:11 +00:00
MerryMage
57c9da1b39 dynarmic: Add Unsafe_InaccurateNaN optimization 2021-01-02 20:13:21 +00:00
ReinUsesLisp
3f048c8646 externals: Update Dynarmic 
Keeps yuzu up to date with the latest changes and introduces a change
needed for a lock-free optimization our side.
 2020-12-29 19:30:52 -03:00
MerryMage
836ec9176a dynarmic: Add unsafe optimizations 2020-08-16 14:15:39 +01:00
MerryMage
0193202964 configuration: Add settings to enable/disable specific CPU optimizations 2020-07-11 14:34:09 +01:00
Fernando Sahmkow
4105f38022 SVC: Implement 32-bits wrappers and update Dynarmic. 2020-06-27 11:36:27 -04:00
Fernando Sahmkow
b8df61c642 ARM: Update Dynarmic and Setup A32 according to latest interface. 2020-06-27 11:36:26 -04:00
Fernando Sahmkow
39ddce1ab5 Externals: Update Dynarmic. 2020-06-27 11:36:19 -04:00
Fernando Sahmkow
3714f2e471 ARMInterface/Externals: Update dynarmic and fit to latest version. 2020-06-27 11:36:13 -04:00
MerryMage
b7a69501cd externals: Update dynarmic to e7166e8b 2020-04-29 14:25:53 +01:00
MerryMage
a3a12deecc dynarmic: Add option to disable CPU JIT optimizations 2020-04-20 13:36:26 +01:00
bunnei
b160804db0 externals: Update to latest dynarmic. 
- Adds memory alignment fixes.
 2020-04-17 00:59:28 -04:00
Markus Wick
0986caa8d8 core/memory + arm/dynarmic: Use a global offset within our arm page table. 
This saves us two x64 instructions per load/store instruction.

TODO: Clean up our memory code. We can use this optimization here as well.
 2020-01-01 12:24:54 +01:00
Ethan
8b76444916 externals: Update dynarmic to master 2019-09-21 16:54:06 +02:00
Lioncash
0964444529 externals: Update dynarmic to master 
Better instruction support has been added since the last update.
 2019-05-07 10:39:25 -04:00
MerryMage
3031aa9d27 externals: Update dynarmic to 4e6848d 
4e6848d A32/ir_emitter: Bugfix: ExceptionRaised was producing incorrect PC
41ba9fd value: Move ImmediateToU64() to be a part of Value's interface
c6a6271 reg_alloc: Emit AVX instructions where able
aedd32a abi: Emit AVX instructions where able
f2d9337 a64_exclusive_monitor: Loosen memory ordering requirements
7ca709d travis: Make macOS builds use Xcode 10
14dd45e Fix VShift terminology
88554c4 emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftS16
ab4e316 emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftS64
0ea84f3 emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftS32
c77a2c5 emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftU16()
e9441fd emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftU64()
0e9c33c emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftU32()
8f85274 emit_x64_vector: SSSE3 variant of EmitVectorCountLeadingZeros8()
be05e75 Merge pull request #397 from VelocityRa/dec-shift-fix
bc328fc decoders: Cast to correctly-sized type before shifting
9c3d2d1 a64_emit_x64: Lowercase PAGE_SIZE
f538d29 emit_x64_vector_floating_point: SSE4.1 implementation of EmitFPVectorToFixed
1603a6e emit_x64_vector_floating_point: EmitFPVectorRoundInt: Use FCODE
2e1ccaf emit_x64_vector: AVX implementation for EmitVectorCountLeadingZeros8
555bfda emit_x64_vector: SSE implementation of EmitVectorCountLeadingZeros16
71c2589 externals: Update Xbyak to 5.73
1ec1b2f Squashed 'externals/xbyak/' changes from 1de435ed..42462ef9
 2018-09-30 19:45:27 +01:00
MerryMage
321eb0b6b0 externals: Update dynarmic to 171d116 
171d116 A64: Implement SCVTF, UCVTF (vector, fixed-point), scalar variant
f221bb0 emit_x64_floating_point: Reduce fallback LUT code in EmitFPToFixed
eb123e2 A64: Implement FCVTZS, FCVTZU, UCVTF, SCVTF (vector, fixed-point), vector variant
487d37a A64: Implement UQSHL's vector immediate and register variants
f698933 ir: Add opcodes for unsigned saturating left shifts
7148e66 A64/translate/impl: Make signatures consistent for unimplemented by-element SIMD variants
fdde4ca A64: Implement BRK
b1490db A64/imm: Add full range of comparison operators to Imm template
1ec40ef IR: Add fbits argument to FPVectorFrom{Signed,Unsigned}Fixed
d6d5e98 A64: Implement SCVTF, UCVTF (scalar, fixed-point)
6513595 opcodes.inc: Align columns to a tabstop of 4
6b0d2b5 IR: Add fbits argument to FixedToFP-related opcodes
c4b3831 A64: Implement SQSHL's vector immediate variant
e0d8d2d A64: Implement SQSHL's vector register variant
5327625 ir: Add opcodes for left signed saturated shifts
9705252 branch: Make variables const where applicable
650946e move_wide: Make variables const where applicable
62b3a6d load_store_register_unprivileged: Make variables const where applicable
3add1c7 load_store_register_immediate: Place conditional bodies on their own line
2fc4088 load_store_load_literal: Make variables const where applicable
b2c1462 data_processing_logical: Move datasize declarations after early-exit conditionals
028028f data_processing_conditional_select: Make variables const where applicable
c66042d data_processing_addsub: Move datasize declarations after early-exit conditionals
6bc546e data_processing_bitfield: Move datasize variables after early-exit conditionals
2aad5fa A64: Implement CLS's vector variant
6c877ff emit_x64_vector: Make EmitVectorUnsignedSaturatedAccumulateSigned() internally linked
4b5926d perf_map: Use std::string_view instead of std::string for PerfMapRegister()
7445947 A64: Implement SQRDMULH (vector), vector variant
03b80f2 A64: Implement SQDMULL (vector), vector variant
4a2c596 IR: Add VectorSignedSaturatedDoublingMultiplyLong
59dc33e emit_x64_vector: Changes to VectorSignedSaturatedDoublingMultiply
bbaebeb IR: Implement Vector{Signed,Unsigned}Multiply{16,32}
baac5a8 backend_x64/a64_interface: Re-enable the constant folding pass
e78ca19 emit_x64_vector_floating_point: Hardware FMA implementation for RSqrtStepFused
8a5ae9a emit_x64_vector_floating_point: Hardware FMA implementation of FPVectorRecipStepFused
39818f9 emit_x64_floating_point: Hardware FMA implementation of FPRSqrtStepFused
3d0a0b4 emit_x64_floating_point: Hardware FMA implementation of FPRecipStepFused{32,64}
2293dff emit_x64_vector: SSE implementation of VectorSignedSaturatedAccumulateUnsigned{8,16,32}
2047683 emit_x64_vector: Correct static asserts for < 64-bit type checks in saturated accumulate fallbacks
55e9e40 emit_x64_vector: EmitVectorSignedSaturatedAccumulateUnsigned64: SSE implementation
1076651 emit_x64_vector: Simplify fpsr_qc related code
4039030 A64: Implement CLZ's vector variant
0bb908f ir: Add opcodes for vector CLZ operations
3b13259 A64/translate: VectorZeroUpper for V(64) stores
1931d44 simd_two_register_misc: FNEG (vector) with Q == 0 had dirty upper
a0790f0 emit_x64_vector: Remove unnecessary [[maybe_unused]] attributes
b0e1eb5 A64: Implement USQADD's scalar and vector variants
28424c7 ir: Add opcodes form unsigned saturated accumulations of signed values
9923ea0 A64: Implement SUQADD's scalar and vector variants
4c0adbb ir: Add opcodes for signed saturated accumulations of unsigned values
799bfed A64: Implement SMLAL{2}, SMLSL{2}, UMLAL{2}, and UMLSL{2}'s vector by-element variants
94451ec A64: Implement UMULL{2}'s vector by-element variant
45867de A64: Implement SMULL{2}'s vector by-element variant
0235793 ir/value: Replace includes with forward declarations
450f721 ir/cond: Migrate to C++17 nested namespace specifiers
e649988 CMakeLists: Add missing cond.h header to file listing
d20e769 A64: Implement URSQRTE
4f3bde5 ir: Add opcodes for performing unsigned reciprocal square root estimates
cfeeaec A64: Implement URECPE
622b60e ir: Add opcodes for unsigned reciprocal estimate
d17599a Update Xbyak to 5.71
f7c26e9 Squashed 'externals/xbyak/' changes from 671fc805..1de435ed
8782b69 travis: Make macOS build with Xcode 9.4.1
b575b23 A64: Implement SQNEG's scalar and vector variant
06062a9 A64: Add opcodes for signed saturating negations
1c40579 emit_x64_vector: Simplify "position == 0" case for EmitVectorExtract()
e335050 emit_x64_vector: Simplify "position == 0" case for EmitVectorExtractLower()
8b13421 A64: Implement SQDMULH's by-element scalar variant
9122a6e A64: Implement SQDMULH's by-element vector variant
176e60e backend/x64: Do not clear fast_dispatch_table if not enabled
 2018-09-19 20:31:39 +01:00
MerryMage
7e9b79955f externals: Update dynarmic to 9594465 
9594465 A64: Implement FastDispatchHint
2be95f2 A32: Implement FastDispatchHint
96f23ac ir/terminal: Add FastDispatchHint
f5ca9e9 A64: Implement SQDMULH's scalar variant
af8bea5 ir: Add opcodes for scalar signed saturated doubling multiplies
fed4220 A64: Implement SQDMULH's vector variant
72eb6ad ir: Add opcodes for signed saturated doubling multiplies
0f8ae84 externals: Update catch to 2.4.0
235165b A64: Implement SQABS' scalar variant
1adca93 A64: Implement SQABS' vector variant.
f978c44 ir: Add opcodes for signed saturated absolute values
d895a84 emit_x64_floating_point: EmitFPToFixed: maxsd optimization
c624fe3 emit_x64_floating_point: ZeroIfNaN: pxor -> xorps
e987a84 IR: Simplify FP{Single,Double}ToFixed{U,S}{32,64}
f1babc8 externals: Update catch to 2.3.0
a0c587a A32/decoder: Add missing <algorithm> includes
 2018-09-07 22:16:50 +01:00
Lioncash
c6fd56b00f
externals: Update dynarmic to 0435ac2 2018-09-03 08:04:24 -04:00
bunnei
c6fda4c758 externals: Update dynarmic to a42f301c. 2018-08-20 19:50:49 -04:00
MerryMage
94329038b6 dynarmic: Update to 550d662 
550d662 load_store_exclusive: Define s == t state to be Constraint_NONE
0b69381 A64/translate: Allow for unpredictable behaviour to be defined
6d236d4 system: Implement MRS CNTFRQ_EL0
6cbb6fb A32/testenv: Add missing headers
6729328 externals: Update xbyak to v5.67
1812bd2 Squashed 'externals/xbyak/' changes from 2794cde7..671fc805
9a95802 externals: Document subtrees
714a840 A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants
8cab459 A64: Implement UQADD/UQSUB's scalar variants
18a8151 ir: Add opcodes for unsigned saturating add and subtract
a5660ee x64/reg_alloc: Use type alias for array returned by GetArgumentInfo()
29489b5 ir/value: Use type alias CoprocessorInfo for std::array<u8, 8>
e23ba26 status_register_access: Add support for bits 0 and 1 of mask to MSR
55190bd fuzz_with_unicorn: Split utility functions into fuzz_util
23b049d A32/translate/load_store: Correct detection of writeback
7ec9f15 A32/translate: Add TranslateSingleInstruction
efeecb4 A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode
08d1d19 A32/decoders: Split instruction list into include file
2d929cc tests: Refactor unicorn_emu to allow for A32 unicorn
f672368 microinstruction: Improve assert messages
7ebff50 emit_x64_vector: EmitVectorNarrow16: AVX512 implementation
edce230 emit_x64_vector: EmitVectorNarrow32: prefer pblendw to loading constant
 2018-08-16 10:12:20 +01:00
MerryMage
ef41983c84 dynarmic: Update to 0118ee0 
0118ee0 emit_x64_vector: packusdw is SSE4.1
 2018-08-10 11:15:04 +01:00
MerryMage
e816745b19 externals: Update dynarmic to 4f96c63 
4f96c63 emit_x64_vector_floating_point: Simplify FPVector{Min,Max}
e15fdfe emit_x64_vector_floating_point: Simplify Get*Vector functions
734a00b emit_x64_floating_point: Remove EmitProcessNaNs
fd45191 devirtualize: Replace DEVIRT macro with function template
67ba5d0 fuzz_with_unicorn: Remove FCVT_float from ignore list
66e6dd1 a32_emit_x64: std::move A32::UserConfig in the constructor
b4890b6 emit_x64_floating_point: Use EmitPostProcessNaNs in EmitFPMulX
18b2943 emit_x64_floating_point: Remove unnecessary DenormalsAreZero from EmitFPSingleToDouble and EmitFPDoubleToSingle
df1f81f emit_x64_floating_point: Simplify EmitFP{Min,Max}{,Numeric}{32,64}
21fb1c3 emit_x64_floating_point: Reduce NaN processing overhead
f5c9f0f A64: Implement FMULX, scalar single/double variant
8f47773 IR: Implement FPMulX IR instruction
79e6440 fuzz_with_unicorn: Randomize SP
33c80e3 fuzz_with_unicorn: Randomize PC
8d41024 testenv: Make code_mem mobile
a9fae0e emit_x64_vector: Vectorize 32-bit variants of paired min/max
8926a92 emit_x64_vector: Improve code emission of VectorGetElement* for index == 0
e20bd38 reg_alloc: Do a UseScratch if a Use destination is too small
a19fa0e fuzz_with_unicorn: Randomize FPCR.AHP and FPCR.FZ16
775f368 emit_x64_floating_point: AVX implementation of ForceToDefaultNaN
71018a1 emit_x64_vector_floating_point: Prefer blendvp{s,d} to vblendvp{s,d} where possible
137f4b3 backend_x64: Remove all use of xmm0
e73d67a emit_x64_vector_floating_point: AVX implementation of ForceToDefaultNaN
43cca54 emit_x64_vector_floating_point: Reduce codesize of ForceToDefaultNaN
5dc40f4 emit_x64_vector_floating_point: Reduce codesize of EmitTwoOpVectorOperation
07622ee emit_x64_vector_floating_point: Correct FMA in FTZ mode
621c85b emit_x64_floating_point: DenormalsAreZero is redundant as hardware already does DAZ
3d0ebaa emit_x64_floating_point: FlushToZero is redundant as hardware already does FTZ
f626ff8 backend_x64: Fix FPVectorMulAdd and FPMulAdd NaN handling with denormals
adeb9d9 a32/fuzz_arm: Disable vfp tests
19ea70d fuzz_with_unicorn: Randomize FPCR.FZ
895db36 backend_x64: Fix bugs when FPCR.FZ=1
d7e2de2 fuzz_with_unicorn: Extract RandomFpcr function
c858d6c fp/info: Deduplicate functions
5b88ec2 emit_x64_floating_point: Deduplicate EmitFPMulAdd implementation
 2018-08-05 17:04:23 +01:00
MerryMage
99b5aa273c externals: Update dynarmic to 73d3efc 
73d3efc emit_x64_floating_point: Deduplicate code
c9508c3 fuzz_with_unicorn: Randomize FPCR.DN
2970833 emit_x64_vector_floating_point: Fix FPVector{Max,Min} when FPCR.DN = 1
150764f emit_x64_floating_point: Fix FP{Max,Min} when FPCR.DN = 1
b7d209c IR: SSE4.1 implementation of FPVectorRoundInt
8cf8270 A64: Implement FRINT{N,M,P,Z,A,X,I} (vector), single/double variant
8f46c26 IR: Initial implementation of FPVectorRoundInt
97017bb A64: Implement SQADD and SQSUB, scalar variant
ce58863 IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths
e80f8ff a64_emit_x64: Bugfix EmitA64OrQC - Incorrect argument
1e4ec7e simd_three_same: Extract non-paired SMAX, SMIN, UMAX, UMIN code to a common function
6f9dc9b A64: Implement SMAXP, SMINP, UMAXP, UMINP
1dfb29f ir: Add opcodes for vector paired maximum and minimums
017b510 A64: Implement SMAXV, SMINV, UMAXV, and UMINV
aae22ee ir: Add opcodes for performing scalar integral min/max
6ef3af3 A64: Implement PMULL{2}
2a4ce19 translate: Deduplicate GetDataSize() functions
0e01500 floating_point_{conditional}_compare: Deduplicate code
259237c common: Move all cryptographic function to common/crypto
c5f1080 a32_emit_x64: BMI2 implementation of A32SetCpsr
a23304a a32_emit_x64: Shorten EmitA32GetCpsr
57604d2 a32_emit_x64: Assert that memory layout assumption in EmitA32GetCpsr is valid
945fa48 A64: Implement PMUL
656a404 ir: Add opcode for performing polynomial multiplication
05143df A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant
34ce767 A64: Implement FCVTZS (vector, integer), single/double variant
0f9bc2d IR: Implement FPVectorTo{Signed,Unsigned}Fixed
0189e44 fp/info: Replace constant value generators with FPValue
db16568 emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min}
31148bd emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs
4c3ca51 A64: Implement FMAX's vector single and double precision variants
bf0f21c A64: Implement FMIN's vector single and double precision variants
76f0ca0 IR: Implement FPVector{Max,Min}
6c37c31 FPRecipEstimate: Move offset out of function
59546f3 microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits
3f6b03a A64: Implement FRECPS, vector/scalar single/double variants
2d2ca5e IR: Implement FPRecipStepFused, FPVectorRecipStepFused
5cb9f1d A64: Implement FRECPE, vector single/double variant
c5a14ab IR: Implement FPVectorRecipEstimate
56f8a0b A64: Implement FRECPE, scalar single/double variant
fde69b4 IR: Implement FPRecipEstimate
186e52c IR: Implement FPRecipEstimate
cf2e1ae fp: Change FPUnpacked to a normalized representation
 2018-07-30 18:23:54 +01:00
MerryMage
abc5b3347d externals: Update dynarmic to 98e2380 
98e2380 fuzz_with_unicorn: Disable testing of FDIV
041b7d5 block_of_code: Add ABI_PARAMS array
2a2371c A64: Implement MLA, MLS (by element), vector single/double variant
78c640a A64: Implement FMLS (vector), single/double variant
b6b6993 emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly
4b9d12a emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused
b1e3616 IR: Implement FPVectorNeg
4343612 A64: Implement FMLA (vector), single/double variant
93eeb25 IR: Implement FPVectorMulAdd
57e5c7e emit_x64_vector_floating_point: Standardize naming scheme
bcb9e41 emit_x64_floating_point: Simplify indexers
83aa585 emit_x64_vector_floating_point: Simplify EmitVectorOperation*
f4087c8 mp: rename mp.h to mp/function_info.h
1864090 emit_x64_vector: Slightly improve ArithmeticShiftRightByte
e048441 emit_x64_vector: Simplify VectorShuffleImpl
ff025e8 IR: Implement A64OrQC
6fac68d A64: Implement UQSHRN, UQRSHRN (vector)
5a8d9c3 emit_x64_vector: -0x80000000 isn't -0x80000000
759289e A64: Implement UQXTN (vector)
2a96281 emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison
0682353 A64: Implement SQXTN (vector)
6c5229e emit_x64_vector: packusdw reqiures SSE4.1
158d9b1 A64: Implement SQSHRUN, SQRSHRUN (vector)
f886013 simd_shift_by_immediate: Simplify ShiftRight
d9b59c6 A64: Implement SQXTUN
50fe28b microinstruction: Reorganize FPSCR related instruction queries
d9d036a microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR()
db96163 u128: Make Bit() a const-qualified member function
f7052ae A64: Implement FRSQRTS (vector), single/double variant
0925ef6 A64: Implement FRSQRTE (vector), single/double variant
f4cbbe3 A64: Implement FRSQRTS (scalar), single/double variant
4ef864e IR: Implement FPRSqrtStepFused
9dffeeb fp: Implement FPRSqrtStepFused
aa04556 fp: Implement FPNeg
cbde1c5 process_nan: Add two operand variant
1ec2663 A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant
027ddf9 emit_x64_floating_point: Fixup special NaN case in FMA FPMulAdd implementation
75a9f77 fp: Use a forward declaration in fused.h
1ee1630 u128: Implement comparison operators in terms of one another
3b77f48 tests: Print cpu info
bed3cc0 u128: StickyLogicalShiftRight requires special-casing for amount == 64
15d04f4 A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant
7cfccdf A64: Implement FMUL (by element)'s scalar double/single-precision variant
7d2d62e (fpmuladd) emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64}
a599eac fp: Implement FPMulAdd
d70b90e process_nan: Add FPProcessNaNs3
38ef0e0 block_of_code: Add SysV ABI fifth and sixth parameters
8e2ff56 u128: Add StickyLogicalShiftRight
3b337df u128: Add Multiply64To128
8219075 u128: Add u128::Bit
a574dcb u128: Add comparison operators
391d6d4 unpacked: Use ResidualErrorOnRightShift in FPRoundBase
5e0cf9c fp: Remove MantissaT
8c0a84c FPRSqrtEstimate: Improve documentation of RecipSqrtEstimate
c41d855 FPRSqrtEstimate: Deduplicate array bounds
4cf055b A64: Implement FMAXV, FMINV, FMAXNMV, and FMINNMV
bf24f0f FPRSqrtEstimate: Use forward declarations where applicable
206230e translate: Return by bool in helpers where applicable
346b725 Simplify fallback case for EmitVectorSetElement64()
2c34e1d emit_x64_floating_point: s/Esimate/Estimate/
5213fb6 simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant
7ed089f IR: Implement FPRSqrtEstimate
cd2e286 simd_vector_x_indexed_element: Implement FMUL (by element), vector variant
 2018-07-25 14:26:51 +01:00
MerryMage
7dde4b7a77 externals: Update dynarmic to fc6b73bd 
Resolves issues:
* 128-bit exclusive writes on Windows
* Non-updating CNTPCT_EL0

fc6b73 a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT
888c67 a64_emit_x64: Fix stack misalignment on Windows for 128-bit exclusive writes
352d53 emit_x64_aes: Eliminate extraneous usage of a scratch register in EmitAESInverseMixColumns()
ab7fe7 A64: Implement SADDLV
09bd2b A64: Implement UADDLV
62e86d fp: Use forward declarations where applicable
b3edb7 emit_x64_vector: Append 'v' prefix onto movq in AVX path
 2018-07-22 16:26:47 +01:00
Lioncash
1519ce7eab
externals: Update dynarmic to 7ea1241 
Resolves an issue with TPIDR setting being erroneously removed in the
dead code pass.
 2018-07-21 13:25:14 -04:00
bunnei
522bd5b736 externals: Update dynarmic to 5a91c94. 2018-07-18 23:14:44 -04:00
Lioncash
0722adb471
externals: Update dynarmic to dfdec79 2018-07-15 16:11:45 -04:00
Lioncash
650c89bbbc
externals: Update dynarmic to f7d11baa1 2018-07-06 20:54:04 -04:00
Lioncash
74efdd6928 externals: Update dynarmic 
Updates dynarmic to revision 990a569b7a5f2518fe08682f5ebf8536e5388d66
 2018-05-23 15:26:23 -04:00
Lioncash
e56e2a1528
externals: Update dynarmic 
Just a basic update to keep it in sync
 2018-04-28 14:31:37 -04:00
Lioncash
b2febaff2f
externals: Update dynarmic to HEAD 2018-04-20 09:02:18 -04:00
MerryMage
57eca6374a dynarmic: Update to 9cc12d8 
9cc12d8 abi: Missing includes
ac35ad5 emit_x64_floating_point: Near jump instead of short jump in FPMinNumberic{32,64}
6f03fdd A64: system: Use an enum class for MRS/MSR register encodings
 2018-03-29 12:49:21 +01:00
MerryMage
78a81614ee dynarmic: Update to 12a1020 
12a1020 emit_X64_floating_point: Near jmp to end instead of short jmp
6278f83 emit_x64_vector: Fix typo in VectorShuffleImpl
25a0204 A64: Implement REV64
aa92e33 bit_util: Do nothing in RotateRight if the rotation amount is zero
e537985 A64: Implement REV32 (vector)
f62a258 ir: Add IR opcodes for emitting vector shuffles
36ac6ec emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64
20a59a9 A64: Implement REV16 (vector)
b2f7bb0 CMakeLists: Add fp_util, macro_util and math_util headers
fd21b58 A64: Implement EOR3 and BCAX
a48c0bb travis: Use yuzu's unicorn fork
59e62e0 externals: Update catch to v2.2.1
 2018-03-27 08:23:35 +01:00
MerryMage
32d127ad3e dynarmic: Update to 6b4c6b0 
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
 2018-02-21 21:39:07 +00:00
FernandoS27
bd6432f1ff updated dynarmic 2018-02-17 14:57:32 -04:00
MerryMage
6085d32cf5 arm_dynarmic: Support direct page table access 2018-02-12 21:53:32 +00:00
MerryMage
45e5a67676 dynarmic: Fix bug due to Windows ABI mismatch 2018-02-09 16:05:28 +00:00
MerryMage
d3bbed5e78 dynarmic: Update to 41ae12263 
Changes: Primarily implementing more A64 instructions
 2018-02-09 00:29:36 +00:00
MerryMage
e7cb20fbf0 externals: Update dynarmic 
a6d17e A64: Implement AND (vector)
963453 tests/A64: Randomize vectors
adcd34 tests/A64/unicorn: Print interrupt number when InterruptHook is hit
304c91 tests/A64: Allow RunTestInstance to start from an arbitrary offset
d333b5 A64: Implement ADD (vector, vector)
1cf87a A64: Implement REV, REV32, and REV16 (#126)
9fc157 IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128
50c181 reg_alloc: GetBitWidth: Add UNREACHABLE
adccbf reg_alloc: Consider bitwidth of data and registers when emitting instructions
7b7f23 A64: Implement CSEL
2f8413 IR: Implement Conditional Select
ebb3e8 A64/tests: Split unicorn sanity checking from other tests
5740a0 tests/A64: Single random instruction: Test branch instructions as well
0892b4 A64/translate/branch: bug: Read-after-write error in BLR
e77bc2 A64: Implement SBFM, BFM, UBFM
0c37ca A64: Implement MOVN, MOVZ, MOVK
b6bb59 travis: Print current test information
e77207 fuzz_thumb: Off by one error
a04ca2 ir/location_descriptor: Add missing <functional> header for std::hash
1e0f5c travis: Run A64 tests
 2018-01-21 22:05:43 +00:00
MerryMage
668e5452fa Update dynarmic to bc73004 
bc73004 a64_merge_interpret_blocks: Remove debug output
4e656ed tests/A64: Randomize PSTATE.<NZCV>
fd9530b A64: Optimization: Merge interpret blocks
3c9eb04 testenv: Use format constants
324f3fc tests/A64: Unicorn interface fixes
98ecbe7 tests/A64: Fuzz against unicorn
b1d38e7 tests/A64: Move TestEnvironment to own header
5218ad9 A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate
b1a8c39 A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31
64827fb a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers
1bfa04d emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64
edadeea A64 inferface: Use two argument static_assert
9ab1304 A64: Add ExceptionRaised IR instruction
6843eed Update readme
7438d07 A64/translate: Add TranslateSingleInstruction function
 2018-01-13 22:38:57 +00:00
MerryMage
106d900f93 dynarmic: Update to 83afe435 2018-01-12 17:49:10 -05:00
MerryMage
d2fbc78320 arm_dynarmic: Implement core 2018-01-12 17:48:29 -05:00
bunnei
d327f66990 externals: Point dynarmic at a real commit. 2018-01-03 21:51:41 -05:00
bunnei
3e80202604 externals: Update dynarmic and xbyak. 2017-10-25 11:26:35 -04:00
bunnei
b1d5db1cf6 Merge remote-tracking branch 'upstream/master' into nx 
# Conflicts:
#	src/core/CMakeLists.txt
#	src/core/arm/dynarmic/arm_dynarmic.cpp
#	src/core/arm/dyncom/arm_dyncom.cpp
#	src/core/hle/kernel/process.cpp
#	src/core/hle/kernel/thread.cpp
#	src/core/hle/kernel/thread.h
#	src/core/hle/kernel/vm_manager.cpp
#	src/core/loader/3dsx.cpp
#	src/core/loader/elf.cpp
#	src/core/loader/ncch.cpp
#	src/core/memory.cpp
#	src/core/memory.h
#	src/core/memory_setup.h
 2017-10-09 23:56:20 -04:00
Yuri Kunde Schlesner
f6715f98f5 Stop using reserved operator names (and/or/xor) with Xbyak 
Also has the Dynarmic upgrade with the same change
 2017-06-17 12:20:22 -07:00
Yuri Kunde Schlesner
4e88458814 Update dynarmic 
Updated to incorporate fix from MerryMage/dynarmic#106 which is required
for using fmt in Citra.
 2017-05-27 14:26:02 -07:00
Emmanuel Gil Peyrot
3a96dd023f dynarmic: Update the submodule. 
This fixes a build issue on gcc 6 due to -Werror and a warning caused
by boost::optional, see:
https://github.com/MerryMage/dynarmic/issues/83
 2017-02-18 14:48:16 +00:00
MerryMage
e2815408fd arm_dynarmic: Update memory interface 2017-02-03 17:32:51 +00:00
MerryMage
2b36d4c9d7 arm_dynarmic: CP15 support 2017-02-03 17:32:47 +00:00
MerryMage
f8cf87ce34 arm_dynarmic: Provide MemoryReadCode callback 
Change of interface in dynarmic 36082087ded632079b16d24137fdd0c450ce82ea
 2016-12-22 16:07:14 +00:00
Yuri Kunde Schlesner
16df1f8078 externals: Update Dynarmic 
Required to be able to use Xbyak in Citra without header conflicts.
 2016-12-14 20:06:08 -08:00
Subv
a088ebe903 Dynarmic: Update dynarmic to version 
54d051977f7a6af9c7596ba6a4e6eb467bd1e0bc

dynarmic log:

54d0519 emit_x64: Use movdqa instead of movaps in EmitPackedSubU8
52e1445 Implement USUB8:33 2016 +0000
5c1aab1 Implement CLZ
1a1646d Implement UADD8
7cad694 IR: Implement new pseudo-operation GetGEFromOp
370f654 fuzz_arm: Add tests for parallel add/subtract (modulo)
25f21b5 emit_x64: Inline nzcv computation into EmitFPCompare32 and EmitFPCompare64
52fdec5 CMakeLists: Add support for LLVM on Windows
cede5e4 emit_x64: Use xorps/xorpd when argument to TransferToFP32/TransferToFP64 is an immediate zero
e166965 Implement VCMP2:33 2016 +0000
f2fe376 Support 64-bit immediates
ff00b8c Document register allocator and return stack buffer optimization
95f34c6 reg_alloc: Remove unnecessary breaks after returns (#54)
dc9707e externals: Update xbyak to 5.32
de1f831 microinstruction: Make use_count private (#53)
3621a92 reg_alloc: Register allocator related constraints belong with the rest of the register allocator
 2016-12-04 21:40:12 -05:00
MerryMage
c46b3dec63 dynarmic: Fix ABI violation 
Caused by not saving/restoring the x64 r15 register on entry/exit from
JITted code.

Closes #2224.
 2016-11-30 19:12:46 +00:00
James Rowe
f32309400c Update dynarmic to the latest version (#2234) 2016-11-29 23:22:19 -05:00
bunnei
1ea1affe0a dynarmic: Add new submodule. 2016-09-15 17:49:25 -04:00