forked from suyu/suyu
bunnei
commit
c4e636681e
4 changed files with 103 additions and 165 deletions
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@ -7,80 +7,77 @@
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#pragma once
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#define FPSID cr0
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#define FPSCR cr1
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#define MVFR1 cr6
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#define MVFR0 cr7
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#define FPEXC cr8
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#define FPINST cr9
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#define FPINST2 cr10
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// FPSID Information
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// Note that these are used as values and not as flags.
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enum : u32 {
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VFP_FPSID_IMPLMEN = 0, // Implementation code. Should be the same as cp15 0 c0 0
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VFP_FPSID_SW = 0, // Software emulation bit value
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VFP_FPSID_SUBARCH = 0x2, // Subarchitecture version number
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VFP_FPSID_PARTNUM = 0x1, // Part number
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VFP_FPSID_VARIANT = 0x1, // Variant number
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VFP_FPSID_REVISION = 0x1 // Revision number
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};
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/* FPSID bits */
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#define FPSID_IMPLEMENTER_BIT (24)
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#define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT)
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#define FPSID_SOFTWARE (1<<23)
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#define FPSID_FORMAT_BIT (21)
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#define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT)
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#define FPSID_NODOUBLE (1<<20)
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#define FPSID_ARCH_BIT (16)
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#define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
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#define FPSID_PART_BIT (8)
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#define FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
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#define FPSID_VARIANT_BIT (4)
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#define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
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#define FPSID_REV_BIT (0)
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#define FPSID_REV_MASK (0xF << FPSID_REV_BIT)
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// FPEXC bits
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enum : u32 {
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FPEXC_EX = (1U << 31U),
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FPEXC_EN = (1 << 30),
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FPEXC_DEX = (1 << 29),
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FPEXC_FP2V = (1 << 28),
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FPEXC_VV = (1 << 27),
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FPEXC_TFV = (1 << 26),
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FPEXC_LENGTH_BIT = (8),
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FPEXC_LENGTH_MASK = (7 << FPEXC_LENGTH_BIT),
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FPEXC_IDF = (1 << 7),
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FPEXC_IXF = (1 << 4),
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FPEXC_UFF = (1 << 3),
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FPEXC_OFF = (1 << 2),
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FPEXC_DZF = (1 << 1),
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FPEXC_IOF = (1 << 0),
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FPEXC_TRAP_MASK = (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
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};
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/* FPEXC bits */
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#define FPEXC_EX (1 << 31)
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#define FPEXC_EN (1 << 30)
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#define FPEXC_DEX (1 << 29)
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#define FPEXC_FP2V (1 << 28)
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#define FPEXC_VV (1 << 27)
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#define FPEXC_TFV (1 << 26)
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#define FPEXC_LENGTH_BIT (8)
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#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
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#define FPEXC_IDF (1 << 7)
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#define FPEXC_IXF (1 << 4)
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#define FPEXC_UFF (1 << 3)
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#define FPEXC_OFF (1 << 2)
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#define FPEXC_DZF (1 << 1)
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#define FPEXC_IOF (1 << 0)
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#define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
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// FPSCR Flags
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enum : u32 {
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FPSCR_NFLAG = (1U << 31U), // Negative condition flag
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FPSCR_ZFLAG = (1 << 30), // Zero condition flag
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FPSCR_CFLAG = (1 << 29), // Carry condition flag
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FPSCR_VFLAG = (1 << 28), // Overflow condition flag
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/* FPSCR bits */
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#define FPSCR_DEFAULT_NAN (1<<25)
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#define FPSCR_FLUSHTOZERO (1<<24)
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#define FPSCR_ROUND_NEAREST (0<<22)
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#define FPSCR_ROUND_PLUSINF (1<<22)
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#define FPSCR_ROUND_MINUSINF (2<<22)
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#define FPSCR_ROUND_TOZERO (3<<22)
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#define FPSCR_RMODE_BIT (22)
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#define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
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#define FPSCR_STRIDE_BIT (20)
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#define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
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#define FPSCR_LENGTH_BIT (16)
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#define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
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#define FPSCR_IOE (1<<8)
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#define FPSCR_DZE (1<<9)
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#define FPSCR_OFE (1<<10)
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#define FPSCR_UFE (1<<11)
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#define FPSCR_IXE (1<<12)
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#define FPSCR_IDE (1<<15)
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#define FPSCR_IOC (1<<0)
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#define FPSCR_DZC (1<<1)
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#define FPSCR_OFC (1<<2)
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#define FPSCR_UFC (1<<3)
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#define FPSCR_IXC (1<<4)
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#define FPSCR_IDC (1<<7)
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FPSCR_QC = (1 << 27), // Cumulative saturation bit
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FPSCR_AHP = (1 << 26), // Alternative half-precision control bit
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FPSCR_DEFAULT_NAN = (1 << 25), // Default NaN mode control bit
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FPSCR_FLUSH_TO_ZERO = (1 << 24), // Flush-to-zero mode control bit
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FPSCR_RMODE_MASK = (3 << 22), // Rounding Mode bit mask
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FPSCR_STRIDE_MASK = (3 << 20), // Vector stride bit mask
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FPSCR_LENGTH_MASK = (7 << 16), // Vector length bit mask
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/* MVFR0 bits */
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#define MVFR0_A_SIMD_BIT (0)
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#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT)
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FPSCR_IDE = (1 << 15), // Input Denormal exception trap enable.
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FPSCR_IXE = (1 << 12), // Inexact exception trap enable
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FPSCR_UFE = (1 << 11), // Undeflow exception trap enable
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FPSCR_OFE = (1 << 10), // Overflow exception trap enable
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FPSCR_DZE = (1 << 9), // Division by Zero exception trap enable
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FPSCR_IOE = (1 << 8), // Invalid Operation exception trap enable
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/* Bit patterns for decoding the packaged operation descriptors */
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#define VFPOPDESC_LENGTH_BIT (9)
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#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)
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#define VFPOPDESC_UNUSED_BIT (24)
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#define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT)
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#define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK))
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FPSCR_IDC = (1 << 7), // Input Denormal cumulative exception bit
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FPSCR_IXC = (1 << 4), // Inexact cumulative exception bit
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FPSCR_UFC = (1 << 3), // Undeflow cumulative exception bit
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FPSCR_OFC = (1 << 2), // Overflow cumulative exception bit
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FPSCR_DZC = (1 << 1), // Division by Zero cumulative exception bit
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FPSCR_IOC = (1 << 0), // Invalid Operation cumulative exception bit
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};
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// FPSCR bit offsets
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enum : u32 {
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FPSCR_RMODE_BIT = 22,
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FPSCR_STRIDE_BIT = 20,
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FPSCR_LENGTH_BIT = 16,
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};
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// FPSCR rounding modes
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enum : u32 {
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FPSCR_ROUND_NEAREST = (0 << 22),
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FPSCR_ROUND_PLUSINF = (1 << 22),
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FPSCR_ROUND_MINUSINF = (2 << 22),
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FPSCR_ROUND_TOZERO = (3 << 22)
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};
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@ -23,6 +23,7 @@
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#include "common/common.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/vfp/asm_vfp.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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//ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */
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@ -27,84 +27,40 @@
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#define CHECK_VFP_ENABLED
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#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); //if (ret == -1) {printf("VFP CDP FAILURE %x\n", inst_cream->instr); exit(-1);}
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unsigned VFPInit (ARMul_State *state);
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unsigned VFPMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value);
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unsigned VFPMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value);
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unsigned VFPMRRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value1, ARMword * value2);
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unsigned VFPMCRR (ARMul_State * state, unsigned type, ARMword instr, ARMword value1, ARMword value2);
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unsigned VFPSTC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value);
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unsigned VFPLDC (ARMul_State * state, unsigned type, ARMword instr, ARMword value);
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unsigned VFPCDP (ARMul_State * state, unsigned type, ARMword instr);
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unsigned VFPInit(ARMul_State* state);
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unsigned VFPMRC(ARMul_State* state, unsigned type, ARMword instr, ARMword* value);
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unsigned VFPMCR(ARMul_State* state, unsigned type, ARMword instr, ARMword value);
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unsigned VFPMRRC(ARMul_State* state, unsigned type, ARMword instr, ARMword* value1, ARMword* value2);
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unsigned VFPMCRR(ARMul_State* state, unsigned type, ARMword instr, ARMword value1, ARMword value2);
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unsigned VFPSTC(ARMul_State* state, unsigned type, ARMword instr, ARMword* value);
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unsigned VFPLDC(ARMul_State* state, unsigned type, ARMword instr, ARMword value);
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unsigned VFPCDP(ARMul_State* state, unsigned type, ARMword instr);
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/* FPSID Information */
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#define VFP_FPSID_IMPLMEN 0 /* should be the same as cp15 0 c0 0*/
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#define VFP_FPSID_SW 0
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#define VFP_FPSID_SUBARCH 0x2 /* VFP version. Current is v3 (not strict) */
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#define VFP_FPSID_PARTNUM 0x1
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#define VFP_FPSID_VARIANT 0x1
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#define VFP_FPSID_REVISION 0x1
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/* FPEXC Flags */
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#define VFP_FPEXC_EX 1<<31
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#define VFP_FPEXC_EN 1<<30
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/* FPSCR Flags */
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#define VFP_FPSCR_NFLAG 1<<31
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#define VFP_FPSCR_ZFLAG 1<<30
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#define VFP_FPSCR_CFLAG 1<<29
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#define VFP_FPSCR_VFLAG 1<<28
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#define VFP_FPSCR_AHP 1<<26 /* Alternative Half Precision */
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#define VFP_FPSCR_DN 1<<25 /* Default NaN */
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#define VFP_FPSCR_FZ 1<<24 /* Flush-to-zero */
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#define VFP_FPSCR_RMODE 3<<22 /* Rounding Mode */
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#define VFP_FPSCR_STRIDE 3<<20 /* Stride (vector) */
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#define VFP_FPSCR_LEN 7<<16 /* Stride (vector) */
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#define VFP_FPSCR_IDE 1<<15 /* Input Denormal exc */
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#define VFP_FPSCR_IXE 1<<12 /* Inexact exc */
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#define VFP_FPSCR_UFE 1<<11 /* Undeflow exc */
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#define VFP_FPSCR_OFE 1<<10 /* Overflow exc */
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#define VFP_FPSCR_DZE 1<<9 /* Division by Zero exc */
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#define VFP_FPSCR_IOE 1<<8 /* Invalid Operation exc */
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#define VFP_FPSCR_IDC 1<<7 /* Input Denormal cum exc */
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#define VFP_FPSCR_IXC 1<<4 /* Inexact cum exc */
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#define VFP_FPSCR_UFC 1<<3 /* Undeflow cum exc */
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#define VFP_FPSCR_OFC 1<<2 /* Overflow cum exc */
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#define VFP_FPSCR_DZC 1<<1 /* Division by Zero cum exc */
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#define VFP_FPSCR_IOC 1<<0 /* Invalid Operation cum exc */
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/* Inline instructions. Note: Used in a cpp file as well */
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#ifdef __cplusplus
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extern "C" {
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#endif
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int32_t vfp_get_float(ARMul_State * state, unsigned int reg);
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void vfp_put_float(ARMul_State * state, int32_t val, unsigned int reg);
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uint64_t vfp_get_double(ARMul_State * state, unsigned int reg);
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void vfp_put_double(ARMul_State * state, uint64_t val, unsigned int reg);
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void vfp_raise_exceptions(ARMul_State * state, uint32_t exceptions, uint32_t inst, uint32_t fpscr);
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s32 vfp_get_float(ARMul_State* state, u32 reg);
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void vfp_put_float(ARMul_State* state, s32 val, u32 reg);
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u64 vfp_get_double(ARMul_State* state, u32 reg);
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void vfp_put_double(ARMul_State* state, u64 val, u32 reg);
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void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr);
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u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
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u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
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/* MRC */
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void VMRS(ARMul_State * state, ARMword reg, ARMword Rt, ARMword *value);
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void VMOVBRS(ARMul_State * state, ARMword to_arm, ARMword t, ARMword n, ARMword *value);
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void VMOVBRRD(ARMul_State * state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword *value1, ARMword *value2);
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// MRC
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void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value);
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void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value);
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void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
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void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
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void VMOVI(ARMul_State * state, ARMword single, ARMword d, ARMword imm);
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void VMOVR(ARMul_State * state, ARMword single, ARMword d, ARMword imm);
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/* MCR */
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void VMSR(ARMul_State * state, ARMword reg, ARMword Rt);
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/* STC */
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int VSTM(ARMul_State * state, int type, ARMword instr, ARMword* value);
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int VPUSH(ARMul_State * state, int type, ARMword instr, ARMword* value);
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int VSTR(ARMul_State * state, int type, ARMword instr, ARMword* value);
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/* LDC */
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int VLDM(ARMul_State * state, int type, ARMword instr, ARMword value);
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int VPOP(ARMul_State * state, int type, ARMword instr, ARMword value);
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int VLDR(ARMul_State * state, int type, ARMword instr, ARMword value);
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void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
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void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
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#ifdef __cplusplus
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}
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#endif
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// MCR
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void VMSR(ARMul_State* state, ARMword reg, ARMword Rt);
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// STC
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int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value);
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int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value);
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int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value);
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// LDC
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int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value);
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int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value);
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int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value);
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@ -239,15 +239,6 @@ struct vfp_single {
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u32 significand;
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern s32 vfp_get_float(ARMul_State * state, unsigned int reg);
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extern void vfp_put_float(ARMul_State * state, s32 val, unsigned int reg);
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#ifdef __cplusplus
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}
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#endif
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/*
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* VFP_SINGLE_MANTISSA_BITS - number of bits in the mantissa
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* VFP_SINGLE_EXPONENT_BITS - number of bits in the exponent
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@ -356,14 +347,7 @@ struct vfp_double {
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#else
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#define VFP_REG_ZERO 16
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern u64 vfp_get_double(ARMul_State * state, unsigned int reg);
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extern void vfp_put_double(ARMul_State * state, u64 val, unsigned int reg);
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#ifdef __cplusplus
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}
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#endif
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#define VFP_DOUBLE_MANTISSA_BITS (52)
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#define VFP_DOUBLE_EXPONENT_BITS (11)
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#define VFP_DOUBLE_LOW_BITS (64 - VFP_DOUBLE_MANTISSA_BITS - 2)
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