forked from suyu/suyu
gl_shader_decompiler: Implement MOV32_IMM instruction.
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parent
3d9126ba87
commit
a7b5ab4d9a
2 changed files with 7 additions and 2 deletions
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@ -290,7 +290,7 @@ public:
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MOV_C,
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MOV_R,
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MOV_IMM,
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MOV32I,
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MOV32_IMM,
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SHR_C,
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SHR_R,
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SHR_IMM,
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@ -445,7 +445,7 @@ private:
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INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"),
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INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
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INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
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INST("000000010000----", Id::MOV32I, Type::Arithmetic, "MOV32I"),
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INST("000000010000----", Id::MOV32_IMM, Type::Arithmetic, "MOV32_IMM"),
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INST("0100110000101---", Id::SHR_C, Type::Arithmetic, "SHR_C"),
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INST("0101110000101---", Id::SHR_R, Type::Arithmetic, "SHR_R"),
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INST("0011100-00101---", Id::SHR_IMM, Type::Arithmetic, "SHR_IMM"),
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@ -620,6 +620,11 @@ private:
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}
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switch (opcode->GetId()) {
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case OpCode::Id::MOV32_IMM: {
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// mov32i doesn't have abs or neg bits.
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regs.SetRegisterToFloat(instr.gpr0, 0, GetImmediate32(instr), 1, 1);
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break;
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}
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case OpCode::Id::FMUL_C:
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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