606 lines
24 KiB
C++
606 lines
24 KiB
C++
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project, 2024 sudachi Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <bit>
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#include <tuple>
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#include <utility>
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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template <typename... Args>
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Id AttrPointer(EmitContext& ctx, Id pointer_type, Id vertex, Id base, Args&&... args) {
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switch (ctx.stage) {
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case Stage::TessellationControl:
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case Stage::TessellationEval:
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case Stage::Geometry:
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return ctx.OpAccessChain(pointer_type, base, vertex, std::forward<Args>(args)...);
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default:
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return ctx.OpAccessChain(pointer_type, base, std::forward<Args>(args)...);
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}
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}
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template <typename... Args>
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Id OutputAccessChain(EmitContext& ctx, Id result_type, Id base, Args&&... args) {
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if (ctx.stage == Stage::TessellationControl) {
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const Id invocation_id{ctx.OpLoad(ctx.U32[1], ctx.invocation_id)};
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return ctx.OpAccessChain(result_type, base, invocation_id, std::forward<Args>(args)...);
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} else {
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return ctx.OpAccessChain(result_type, base, std::forward<Args>(args)...);
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}
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}
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struct OutAttr {
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OutAttr(Id pointer_) : pointer{pointer_} {}
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OutAttr(Id pointer_, Id type_) : pointer{pointer_}, type{type_} {}
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Id pointer{};
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Id type{};
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};
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std::optional<OutAttr> OutputAttrPointer(EmitContext& ctx, IR::Attribute attr) {
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if (IR::IsGeneric(attr)) {
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const u32 index{IR::GenericAttributeIndex(attr)};
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const u32 element{IR::GenericAttributeElement(attr)};
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const GenericElementInfo& info{ctx.output_generics.at(index).at(element)};
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if (info.num_components == 1) {
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return info.id;
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} else {
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const u32 index_element{element - info.first_element};
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const Id index_id{ctx.Const(index_element)};
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return OutputAccessChain(ctx, ctx.output_f32, info.id, index_id);
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}
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}
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switch (attr) {
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case IR::Attribute::PointSize:
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return ctx.output_point_size;
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case IR::Attribute::PositionX:
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case IR::Attribute::PositionY:
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case IR::Attribute::PositionZ:
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case IR::Attribute::PositionW: {
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const u32 element{static_cast<u32>(attr) % 4};
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const Id element_id{ctx.Const(element)};
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return OutputAccessChain(ctx, ctx.output_f32, ctx.output_position, element_id);
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}
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case IR::Attribute::ClipDistance0:
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case IR::Attribute::ClipDistance1:
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case IR::Attribute::ClipDistance2:
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case IR::Attribute::ClipDistance3:
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case IR::Attribute::ClipDistance4:
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case IR::Attribute::ClipDistance5:
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case IR::Attribute::ClipDistance6:
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case IR::Attribute::ClipDistance7: {
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const u32 base{static_cast<u32>(IR::Attribute::ClipDistance0)};
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const u32 index{static_cast<u32>(attr) - base};
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if (index >= ctx.profile.max_user_clip_distances) {
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LOG_WARNING(Shader, "Ignoring clip distance store {} >= {} supported", index,
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ctx.profile.max_user_clip_distances);
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return std::nullopt;
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}
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const Id clip_num{ctx.Const(index)};
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return OutputAccessChain(ctx, ctx.output_f32, ctx.clip_distances, clip_num);
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}
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case IR::Attribute::Layer:
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if (ctx.profile.support_viewport_index_layer_non_geometry ||
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ctx.stage == Shader::Stage::Geometry) {
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return OutAttr{ctx.layer, ctx.U32[1]};
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}
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return std::nullopt;
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case IR::Attribute::ViewportIndex:
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if (!ctx.profile.support_multi_viewport) {
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LOG_WARNING(Shader, "Ignoring viewport index store on non-supporting driver");
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return std::nullopt;
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}
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if (ctx.profile.support_viewport_index_layer_non_geometry ||
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ctx.stage == Shader::Stage::Geometry) {
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return OutAttr{ctx.viewport_index, ctx.U32[1]};
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}
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return std::nullopt;
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case IR::Attribute::ViewportMask:
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if (!ctx.profile.support_viewport_mask) {
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return std::nullopt;
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}
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return OutAttr{ctx.OpAccessChain(ctx.output_u32, ctx.viewport_mask, ctx.u32_zero_value),
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ctx.U32[1]};
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default:
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throw NotImplementedException("Read attribute {}", attr);
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}
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}
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Id GetCbuf(EmitContext& ctx, Id result_type, Id UniformDefinitions::*member_ptr, u32 element_size,
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const IR::Value& binding, const IR::Value& offset, const Id indirect_func) {
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Id buffer_offset;
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const Id uniform_type{ctx.uniform_types.*member_ptr};
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if (offset.IsImmediate()) {
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// Hardware been proved to read the aligned offset (e.g. LDC.U32 at 6 will read offset 4)
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const Id imm_offset{ctx.Const(offset.U32() / element_size)};
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buffer_offset = imm_offset;
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} else if (element_size > 1) {
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const u32 log2_element_size{static_cast<u32>(std::countr_zero(element_size))};
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const Id shift{ctx.Const(log2_element_size)};
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buffer_offset = ctx.OpShiftRightLogical(ctx.U32[1], ctx.Def(offset), shift);
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} else {
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buffer_offset = ctx.Def(offset);
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}
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if (!binding.IsImmediate()) {
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return ctx.OpFunctionCall(result_type, indirect_func, ctx.Def(binding), buffer_offset);
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}
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const Id cbuf{ctx.cbufs[binding.U32()].*member_ptr};
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const Id access_chain{ctx.OpAccessChain(uniform_type, cbuf, ctx.u32_zero_value, buffer_offset)};
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const Id val = ctx.OpLoad(result_type, access_chain);
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if (offset.IsImmediate() || !ctx.profile.has_broken_robust) {
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return val;
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}
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const auto is_float = UniformDefinitions::IsFloat(member_ptr);
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const auto num_elements = UniformDefinitions::NumElements(member_ptr);
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const std::array zero_vec{
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is_float ? ctx.Const(0.0f) : ctx.Const(0u),
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is_float ? ctx.Const(0.0f) : ctx.Const(0u),
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is_float ? ctx.Const(0.0f) : ctx.Const(0u),
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is_float ? ctx.Const(0.0f) : ctx.Const(0u),
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};
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const Id cond = ctx.OpULessThanEqual(ctx.TypeBool(), buffer_offset, ctx.Const(0xFFFFu));
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const Id zero = ctx.OpCompositeConstruct(result_type, std::span(zero_vec.data(), num_elements));
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return ctx.OpSelect(result_type, cond, val, zero);
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}
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Id GetCbufU32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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return GetCbuf(ctx, ctx.U32[1], &UniformDefinitions::U32, sizeof(u32), binding, offset,
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ctx.load_const_func_u32);
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}
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Id GetCbufU32x4(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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return GetCbuf(ctx, ctx.U32[4], &UniformDefinitions::U32x4, sizeof(u32[4]), binding, offset,
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ctx.load_const_func_u32x4);
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}
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Id GetCbufElement(EmitContext& ctx, Id vector, const IR::Value& offset, u32 index_offset) {
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if (offset.IsImmediate()) {
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const u32 element{(offset.U32() / 4) % 4 + index_offset};
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return ctx.OpCompositeExtract(ctx.U32[1], vector, element);
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}
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const Id shift{ctx.OpShiftRightLogical(ctx.U32[1], ctx.Def(offset), ctx.Const(2u))};
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Id element{ctx.OpBitwiseAnd(ctx.U32[1], shift, ctx.Const(3u))};
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if (index_offset > 0) {
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element = ctx.OpIAdd(ctx.U32[1], element, ctx.Const(index_offset));
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}
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return ctx.OpVectorExtractDynamic(ctx.U32[1], vector, element);
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}
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} // Anonymous namespace
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void EmitGetRegister(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitSetRegister(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitGetPred(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitSetPred(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitSetGotoVariable(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitGetGotoVariable(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitSetIndirectBranchVariable(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitGetIndirectBranchVariable(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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Id EmitGetCbufU8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_descriptor_aliasing && ctx.profile.support_int8) {
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const Id load{GetCbuf(ctx, ctx.U8, &UniformDefinitions::U8, sizeof(u8), binding, offset,
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ctx.load_const_func_u8)};
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return ctx.OpUConvert(ctx.U32[1], load);
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}
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Id element{};
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if (ctx.profile.support_descriptor_aliasing) {
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element = GetCbufU32(ctx, binding, offset);
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} else {
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const Id vector{GetCbufU32x4(ctx, binding, offset)};
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element = GetCbufElement(ctx, vector, offset, 0u);
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}
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const Id bit_offset{ctx.BitOffset8(offset)};
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return ctx.OpBitFieldUExtract(ctx.U32[1], element, bit_offset, ctx.Const(8u));
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}
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Id EmitGetCbufS8(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_descriptor_aliasing && ctx.profile.support_int8) {
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const Id load{GetCbuf(ctx, ctx.S8, &UniformDefinitions::S8, sizeof(s8), binding, offset,
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ctx.load_const_func_u8)};
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return ctx.OpSConvert(ctx.U32[1], load);
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}
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Id element{};
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if (ctx.profile.support_descriptor_aliasing) {
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element = GetCbufU32(ctx, binding, offset);
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} else {
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const Id vector{GetCbufU32x4(ctx, binding, offset)};
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element = GetCbufElement(ctx, vector, offset, 0u);
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}
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const Id bit_offset{ctx.BitOffset8(offset)};
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return ctx.OpBitFieldSExtract(ctx.U32[1], element, bit_offset, ctx.Const(8u));
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}
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Id EmitGetCbufU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_descriptor_aliasing && ctx.profile.support_int16) {
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const Id load{GetCbuf(ctx, ctx.U16, &UniformDefinitions::U16, sizeof(u16), binding, offset,
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ctx.load_const_func_u16)};
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return ctx.OpUConvert(ctx.U32[1], load);
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}
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Id element{};
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if (ctx.profile.support_descriptor_aliasing) {
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element = GetCbufU32(ctx, binding, offset);
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} else {
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const Id vector{GetCbufU32x4(ctx, binding, offset)};
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element = GetCbufElement(ctx, vector, offset, 0u);
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}
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const Id bit_offset{ctx.BitOffset16(offset)};
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return ctx.OpBitFieldUExtract(ctx.U32[1], element, bit_offset, ctx.Const(16u));
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}
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Id EmitGetCbufS16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_descriptor_aliasing && ctx.profile.support_int16) {
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const Id load{GetCbuf(ctx, ctx.S16, &UniformDefinitions::S16, sizeof(s16), binding, offset,
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ctx.load_const_func_u16)};
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return ctx.OpSConvert(ctx.U32[1], load);
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}
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Id element{};
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if (ctx.profile.support_descriptor_aliasing) {
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element = GetCbufU32(ctx, binding, offset);
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} else {
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const Id vector{GetCbufU32x4(ctx, binding, offset)};
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element = GetCbufElement(ctx, vector, offset, 0u);
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}
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const Id bit_offset{ctx.BitOffset16(offset)};
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return ctx.OpBitFieldSExtract(ctx.U32[1], element, bit_offset, ctx.Const(16u));
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}
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Id EmitGetCbufU32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_descriptor_aliasing) {
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return GetCbufU32(ctx, binding, offset);
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} else {
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const Id vector{GetCbufU32x4(ctx, binding, offset)};
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return GetCbufElement(ctx, vector, offset, 0u);
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}
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}
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Id EmitGetCbufF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_descriptor_aliasing) {
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return GetCbuf(ctx, ctx.F32[1], &UniformDefinitions::F32, sizeof(f32), binding, offset,
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ctx.load_const_func_f32);
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} else {
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const Id vector{GetCbufU32x4(ctx, binding, offset)};
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return ctx.OpBitcast(ctx.F32[1], GetCbufElement(ctx, vector, offset, 0u));
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}
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}
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Id EmitGetCbufU32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (ctx.profile.support_descriptor_aliasing) {
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return GetCbuf(ctx, ctx.U32[2], &UniformDefinitions::U32x2, sizeof(u32[2]), binding, offset,
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ctx.load_const_func_u32x2);
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} else {
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const Id vector{GetCbufU32x4(ctx, binding, offset)};
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return ctx.OpCompositeConstruct(ctx.U32[2], GetCbufElement(ctx, vector, offset, 0u),
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GetCbufElement(ctx, vector, offset, 1u));
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}
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}
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, Id vertex) {
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const u32 element{static_cast<u32>(attr) % 4};
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if (IR::IsGeneric(attr)) {
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const u32 index{IR::GenericAttributeIndex(attr)};
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const auto& generic{ctx.input_generics.at(index)};
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if (!ValidId(generic.id)) {
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// Attribute is disabled or varying component is not written
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return ctx.Const(element == 3 ? 1.0f : 0.0f);
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}
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const Id pointer{
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AttrPointer(ctx, generic.pointer_type, vertex, generic.id, ctx.Const(element))};
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const Id value{ctx.OpLoad(generic.component_type, pointer)};
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return [&ctx, generic, value]() {
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switch (generic.load_op) {
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case InputGenericLoadOp::Bitcast:
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return ctx.OpBitcast(ctx.F32[1], value);
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case InputGenericLoadOp::SToF:
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return ctx.OpConvertSToF(ctx.F32[1], value);
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case InputGenericLoadOp::UToF:
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return ctx.OpConvertUToF(ctx.F32[1], value);
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default:
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return value;
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};
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}();
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}
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switch (attr) {
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case IR::Attribute::PrimitiveId:
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.primitive_id));
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case IR::Attribute::Layer:
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.layer));
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case IR::Attribute::PositionX:
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case IR::Attribute::PositionY:
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case IR::Attribute::PositionZ:
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case IR::Attribute::PositionW:
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return ctx.OpLoad(
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ctx.F32[1],
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ctx.need_input_position_indirect
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? AttrPointer(ctx, ctx.input_f32, vertex, ctx.input_position, ctx.u32_zero_value,
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ctx.Const(element))
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: AttrPointer(ctx, ctx.input_f32, vertex, ctx.input_position, ctx.Const(element)));
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case IR::Attribute::InstanceId:
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if (ctx.profile.support_vertex_instance_id) {
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.instance_id));
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} else {
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const Id index{ctx.OpLoad(ctx.U32[1], ctx.instance_index)};
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const Id base{ctx.OpLoad(ctx.U32[1], ctx.base_instance)};
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return ctx.OpBitcast(ctx.F32[1], ctx.OpISub(ctx.U32[1], index, base));
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}
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case IR::Attribute::VertexId:
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if (ctx.profile.support_vertex_instance_id) {
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.vertex_id));
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} else {
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.vertex_index));
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}
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case IR::Attribute::BaseInstance:
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.base_instance));
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case IR::Attribute::BaseVertex:
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.base_vertex));
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case IR::Attribute::DrawID:
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.draw_index));
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case IR::Attribute::FrontFace:
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return ctx.OpSelect(ctx.F32[1], ctx.OpLoad(ctx.U1, ctx.front_face),
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ctx.OpBitcast(ctx.F32[1], ctx.Const(std::numeric_limits<u32>::max())),
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ctx.f32_zero_value);
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case IR::Attribute::PointSpriteS:
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return ctx.OpLoad(ctx.F32[1],
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ctx.OpAccessChain(ctx.input_f32, ctx.point_coord, ctx.u32_zero_value));
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case IR::Attribute::PointSpriteT:
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return ctx.OpLoad(ctx.F32[1],
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ctx.OpAccessChain(ctx.input_f32, ctx.point_coord, ctx.Const(1U)));
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case IR::Attribute::TessellationEvaluationPointU:
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return ctx.OpLoad(ctx.F32[1],
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ctx.OpAccessChain(ctx.input_f32, ctx.tess_coord, ctx.u32_zero_value));
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case IR::Attribute::TessellationEvaluationPointV:
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return ctx.OpLoad(ctx.F32[1],
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ctx.OpAccessChain(ctx.input_f32, ctx.tess_coord, ctx.Const(1U)));
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default:
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throw NotImplementedException("Read attribute {}", attr);
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}
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}
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Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, Id) {
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switch (attr) {
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case IR::Attribute::PrimitiveId:
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return ctx.OpLoad(ctx.U32[1], ctx.primitive_id);
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case IR::Attribute::InstanceId:
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if (ctx.profile.support_vertex_instance_id) {
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return ctx.OpLoad(ctx.U32[1], ctx.instance_id);
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} else {
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const Id index{ctx.OpLoad(ctx.U32[1], ctx.instance_index)};
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const Id base{ctx.OpLoad(ctx.U32[1], ctx.base_instance)};
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return ctx.OpISub(ctx.U32[1], index, base);
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}
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case IR::Attribute::VertexId:
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if (ctx.profile.support_vertex_instance_id) {
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return ctx.OpLoad(ctx.U32[1], ctx.vertex_id);
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} else {
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return ctx.OpLoad(ctx.U32[1], ctx.vertex_index);
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}
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case IR::Attribute::BaseInstance:
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return ctx.OpLoad(ctx.U32[1], ctx.base_instance);
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case IR::Attribute::BaseVertex:
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return ctx.OpLoad(ctx.U32[1], ctx.base_vertex);
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case IR::Attribute::DrawID:
|
|
return ctx.OpLoad(ctx.U32[1], ctx.draw_index);
|
|
default:
|
|
throw NotImplementedException("Read U32 attribute {}", attr);
|
|
}
|
|
}
|
|
|
|
void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, [[maybe_unused]] Id vertex) {
|
|
const std::optional<OutAttr> output{OutputAttrPointer(ctx, attr)};
|
|
if (!output) {
|
|
return;
|
|
}
|
|
if (Sirit::ValidId(output->type)) {
|
|
value = ctx.OpBitcast(output->type, value);
|
|
}
|
|
ctx.OpStore(output->pointer, value);
|
|
}
|
|
|
|
Id EmitGetAttributeIndexed(EmitContext& ctx, Id offset, Id vertex) {
|
|
switch (ctx.stage) {
|
|
case Stage::TessellationControl:
|
|
case Stage::TessellationEval:
|
|
case Stage::Geometry:
|
|
return ctx.OpFunctionCall(ctx.F32[1], ctx.indexed_load_func, offset, vertex);
|
|
default:
|
|
return ctx.OpFunctionCall(ctx.F32[1], ctx.indexed_load_func, offset);
|
|
}
|
|
}
|
|
|
|
void EmitSetAttributeIndexed(EmitContext& ctx, Id offset, Id value, [[maybe_unused]] Id vertex) {
|
|
ctx.OpFunctionCall(ctx.void_id, ctx.indexed_store_func, offset, value);
|
|
}
|
|
|
|
Id EmitGetPatch(EmitContext& ctx, IR::Patch patch) {
|
|
if (!IR::IsGeneric(patch)) {
|
|
throw NotImplementedException("Non-generic patch load");
|
|
}
|
|
const u32 index{IR::GenericPatchIndex(patch)};
|
|
const Id element{ctx.Const(IR::GenericPatchElement(patch))};
|
|
const Id type{ctx.stage == Stage::TessellationControl ? ctx.output_f32 : ctx.input_f32};
|
|
const Id pointer{ctx.OpAccessChain(type, ctx.patches.at(index), element)};
|
|
return ctx.OpLoad(ctx.F32[1], pointer);
|
|
}
|
|
|
|
void EmitSetPatch(EmitContext& ctx, IR::Patch patch, Id value) {
|
|
const Id pointer{[&] {
|
|
if (IR::IsGeneric(patch)) {
|
|
const u32 index{IR::GenericPatchIndex(patch)};
|
|
const Id element{ctx.Const(IR::GenericPatchElement(patch))};
|
|
return ctx.OpAccessChain(ctx.output_f32, ctx.patches.at(index), element);
|
|
}
|
|
switch (patch) {
|
|
case IR::Patch::TessellationLodLeft:
|
|
case IR::Patch::TessellationLodRight:
|
|
case IR::Patch::TessellationLodTop:
|
|
case IR::Patch::TessellationLodBottom: {
|
|
const u32 index{static_cast<u32>(patch) - u32(IR::Patch::TessellationLodLeft)};
|
|
const Id index_id{ctx.Const(index)};
|
|
return ctx.OpAccessChain(ctx.output_f32, ctx.output_tess_level_outer, index_id);
|
|
}
|
|
case IR::Patch::TessellationLodInteriorU:
|
|
return ctx.OpAccessChain(ctx.output_f32, ctx.output_tess_level_inner,
|
|
ctx.u32_zero_value);
|
|
case IR::Patch::TessellationLodInteriorV:
|
|
return ctx.OpAccessChain(ctx.output_f32, ctx.output_tess_level_inner, ctx.Const(1u));
|
|
default:
|
|
throw NotImplementedException("Patch {}", patch);
|
|
}
|
|
}()};
|
|
ctx.OpStore(pointer, value);
|
|
}
|
|
|
|
void EmitSetFragColor(EmitContext& ctx, u32 index, u32 component, Id value) {
|
|
const Id component_id{ctx.Const(component)};
|
|
const Id pointer{ctx.OpAccessChain(ctx.output_f32, ctx.frag_color.at(index), component_id)};
|
|
ctx.OpStore(pointer, value);
|
|
}
|
|
|
|
void EmitSetSampleMask(EmitContext& ctx, Id value) {
|
|
const Id pointer{ctx.OpAccessChain(ctx.output_u32, ctx.sample_mask, ctx.u32_zero_value)};
|
|
ctx.OpStore(pointer, value);
|
|
}
|
|
|
|
void EmitSetFragDepth(EmitContext& ctx, Id value) {
|
|
if (!ctx.runtime_info.convert_depth_mode || ctx.profile.support_native_ndc) {
|
|
ctx.OpStore(ctx.frag_depth, value);
|
|
return;
|
|
}
|
|
const Id unit{ctx.Const(0.5f)};
|
|
const Id new_depth{ctx.OpFma(ctx.F32[1], value, unit, unit)};
|
|
ctx.OpStore(ctx.frag_depth, new_depth);
|
|
}
|
|
|
|
void EmitGetZFlag(EmitContext&) {
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
}
|
|
|
|
void EmitGetSFlag(EmitContext&) {
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
}
|
|
|
|
void EmitGetCFlag(EmitContext&) {
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
}
|
|
|
|
void EmitGetOFlag(EmitContext&) {
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
}
|
|
|
|
void EmitSetZFlag(EmitContext&) {
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
}
|
|
|
|
void EmitSetSFlag(EmitContext&) {
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
}
|
|
|
|
void EmitSetCFlag(EmitContext&) {
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
}
|
|
|
|
void EmitSetOFlag(EmitContext&) {
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
}
|
|
|
|
Id EmitWorkgroupId(EmitContext& ctx) {
|
|
return ctx.OpLoad(ctx.U32[3], ctx.workgroup_id);
|
|
}
|
|
|
|
Id EmitLocalInvocationId(EmitContext& ctx) {
|
|
return ctx.OpLoad(ctx.U32[3], ctx.local_invocation_id);
|
|
}
|
|
|
|
Id EmitInvocationId(EmitContext& ctx) {
|
|
return ctx.OpLoad(ctx.U32[1], ctx.invocation_id);
|
|
}
|
|
|
|
Id EmitInvocationInfo(EmitContext& ctx) {
|
|
switch (ctx.stage) {
|
|
case Stage::TessellationControl:
|
|
case Stage::TessellationEval:
|
|
return ctx.OpShiftLeftLogical(ctx.U32[1], ctx.OpLoad(ctx.U32[1], ctx.patch_vertices_in),
|
|
ctx.Const(16u));
|
|
case Stage::Geometry:
|
|
return ctx.Const(InputTopologyVertices::vertices(ctx.runtime_info.input_topology) << 16);
|
|
default:
|
|
LOG_WARNING(Shader, "(STUBBED) called");
|
|
return ctx.Const(0x00ff0000u);
|
|
}
|
|
}
|
|
|
|
Id EmitSampleId(EmitContext& ctx) {
|
|
return ctx.OpLoad(ctx.U32[1], ctx.sample_id);
|
|
}
|
|
|
|
Id EmitIsHelperInvocation(EmitContext& ctx) {
|
|
return ctx.OpLoad(ctx.U1, ctx.is_helper_invocation);
|
|
}
|
|
|
|
Id EmitYDirection(EmitContext& ctx) {
|
|
return ctx.Const(ctx.runtime_info.y_negate ? -1.0f : 1.0f);
|
|
}
|
|
|
|
Id EmitResolutionDownFactor(EmitContext& ctx) {
|
|
if (ctx.profile.unified_descriptor_binding) {
|
|
const Id pointer_type{ctx.TypePointer(spv::StorageClass::PushConstant, ctx.F32[1])};
|
|
const Id index{ctx.Const(ctx.rescaling_downfactor_member_index)};
|
|
const Id pointer{ctx.OpAccessChain(pointer_type, ctx.rescaling_push_constants, index)};
|
|
return ctx.OpLoad(ctx.F32[1], pointer);
|
|
} else {
|
|
const Id composite{ctx.OpLoad(ctx.F32[4], ctx.rescaling_uniform_constant)};
|
|
return ctx.OpCompositeExtract(ctx.F32[1], composite, 2u);
|
|
}
|
|
}
|
|
|
|
Id EmitRenderArea(EmitContext& ctx) {
|
|
if (ctx.profile.unified_descriptor_binding) {
|
|
const Id pointer_type{ctx.TypePointer(spv::StorageClass::PushConstant, ctx.F32[4])};
|
|
const Id index{ctx.Const(ctx.render_are_member_index)};
|
|
const Id pointer{ctx.OpAccessChain(pointer_type, ctx.render_area_push_constant, index)};
|
|
return ctx.OpLoad(ctx.F32[4], pointer);
|
|
} else {
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
}
|
|
}
|
|
|
|
Id EmitLoadLocal(EmitContext& ctx, Id word_offset) {
|
|
const Id pointer{ctx.OpAccessChain(ctx.private_u32, ctx.local_memory, word_offset)};
|
|
return ctx.OpLoad(ctx.U32[1], pointer);
|
|
}
|
|
|
|
void EmitWriteLocal(EmitContext& ctx, Id word_offset, Id value) {
|
|
const Id pointer{ctx.OpAccessChain(ctx.private_u32, ctx.local_memory, word_offset)};
|
|
ctx.OpStore(pointer, value);
|
|
}
|
|
|
|
} // namespace Shader::Backend::SPIRV
|