128 lines
4.5 KiB
C++
128 lines
4.5 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <array>
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#include <cstddef>
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#include <memory>
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#include <utility>
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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#include "common/vector_math.h"
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#include "core/memory.h"
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#include "core/tracer/recorder.h"
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#include "video_core/command_processor.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_compute.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/gpu.h"
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#include "video_core/renderer_base.h"
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#include "video_core/video_core.h"
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namespace Tegra {
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enum class BufferMethods {
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BindObject = 0,
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CountBufferMethods = 0x40,
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};
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void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params) {
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LOG_WARNING(HW_GPU,
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"Processing method {:08X} on subchannel {} value "
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"{:08X} remaining params {}",
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method, subchannel, value, remaining_params);
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if (method == static_cast<u32>(BufferMethods::BindObject)) {
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// Bind the current subchannel to the desired engine id.
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LOG_DEBUG(HW_GPU, "Binding subchannel {} to engine {}", subchannel, value);
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bound_engines[subchannel] = static_cast<EngineID>(value);
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return;
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}
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if (method < static_cast<u32>(BufferMethods::CountBufferMethods)) {
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// TODO(Subv): Research and implement these methods.
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LOG_ERROR(HW_GPU, "Special buffer methods other than Bind are not implemented");
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return;
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}
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ASSERT(bound_engines.find(subchannel) != bound_engines.end());
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const EngineID engine = bound_engines[subchannel];
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switch (engine) {
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case EngineID::FERMI_TWOD_A:
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fermi_2d->WriteReg(method, value);
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break;
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case EngineID::MAXWELL_B:
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maxwell_3d->WriteReg(method, value, remaining_params);
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break;
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case EngineID::MAXWELL_COMPUTE_B:
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maxwell_compute->WriteReg(method, value);
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break;
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case EngineID::MAXWELL_DMA_COPY_A:
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maxwell_dma->WriteReg(method, value);
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break;
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default:
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UNIMPLEMENTED_MSG("Unimplemented engine");
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}
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}
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void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
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const boost::optional<VAddr> head_address = memory_manager->GpuToCpuAddress(address);
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VAddr current_addr = *head_address;
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while (current_addr < *head_address + size * sizeof(CommandHeader)) {
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const CommandHeader header = {Memory::Read32(current_addr)};
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current_addr += sizeof(u32);
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switch (header.mode.Value()) {
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case SubmissionMode::IncreasingOld:
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case SubmissionMode::Increasing: {
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// Increase the method value with each argument.
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for (unsigned i = 0; i < header.arg_count; ++i) {
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WriteReg(header.method + i, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - i - 1);
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current_addr += sizeof(u32);
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}
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break;
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}
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case SubmissionMode::NonIncreasingOld:
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case SubmissionMode::NonIncreasing: {
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// Use the same method value for all arguments.
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for (unsigned i = 0; i < header.arg_count; ++i) {
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WriteReg(header.method, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - i - 1);
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current_addr += sizeof(u32);
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}
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break;
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}
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case SubmissionMode::IncreaseOnce: {
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ASSERT(header.arg_count.Value() >= 1);
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// Use the original method for the first argument and then the next method for all other
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// arguments.
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WriteReg(header.method, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - 1);
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current_addr += sizeof(u32);
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for (unsigned i = 1; i < header.arg_count; ++i) {
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WriteReg(header.method + 1, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - i - 1);
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current_addr += sizeof(u32);
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}
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break;
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}
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case SubmissionMode::Inline: {
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// The register value is stored in the bits 16-28 as an immediate
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WriteReg(header.method, header.subchannel, header.inline_data, 0);
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break;
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}
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default:
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UNIMPLEMENTED();
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}
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}
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}
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} // namespace Tegra
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