fdf626b74f
2ce465bbc Merge branch 'dev'
0b3f360eb v7.05
66f22b7a4 update doc
13ee4e19f use opSetCC for setCC
383866b42 use opMR with APX
d6e6e6f85 tweak
a7b02ac80 RAO_INT supports APX
26840492c use Address.immSize
e2b40a33e refactor Address class
e1b6896c2 Merge branch 'dev'
c0888cc45 v7.04
7d9c82835 refactor rex
b3e27734b apx supports 0x0f opecode with rex2
2e7b62d78 bswap supports apx
2e93baa6a Merge branch 'dev'
e1864642c unify getMap and getMMM
0750873b7 T_MAP3 is not necessary
ee4984222 T_MAP1 is not necessary
5c95842be tweak
8c44467af add no_flags sample
523cf1ed0 fix comment of sample/ccmp.cpp
5438fc69d Merge branch 'dev'
ee26c094e v7.03
691ce361a [doc] update dfv
8d0e78146 set 0 for the default value of dfv
2255aea0d [doc] add ccmpSCC and ctestSCC
b5e115284 add sample/ccmp.cpp
bacd8d34b add sample/zero_upper.cpp
f17cb9d6b Merge branch 'dev'
c9ce3f8f6 v7.02
3427be298 unify opAESKL and opSHA
bfd14244a update doc
e690a2a47 sha* supports apx
c9765588f Merge branch 'dev'
903f7c02e v7.01
54a1f07f9 update cpuid by sde
223ddfaf8 add detection of sse4a/clwb
ba943b5b6 reorder cpu detection
30c362df5 Merge branch 'Sonicadvance1-missing_checks' into dev
02bc84ad8 renumber of tSSE4a, tCLWB
84fe3ab9d update doc
90fc0151c add encodekey{128,256}
440972b88 add detection of KEYLOCKER, KEYLOCKER_WIDE
68a30b91f add detection of AESKLE, WIDE_KL
e2d36c662 fix detection of AVX10
48551f5cc add aesenc{128,256}kl, aesencwide{128,256}kl
d9c7c992f add aesdecwide{128,256}kl
cd5231de0 add aesdec256kl
fcb3d0dbb add aesdec128kl
85709ace7 mvoe opKmov in private
406199e7a Support cpuid CLWB
1214aad95 Adds back missing SSE4a check
5315658ad add detection of avx10/apx_f
835f6d2e6 Merge pull request #180 from Tachi107/fix-32bit-tests
650b241e3 test: only run apx test when BIT=64
016ce86b6 [doc] add a blank line
df0ebc740 v7.00
1ec2adbbb Merge branch 'apx'
da1818592 update doc
bec145ba9 amx supports apx
944438195 add tests of kmov*
bd85d108c kmov* supports apx
93bd6a0b7 rename T_VEX to T_APX
b063d276f add misc tests
6d21c7389 add evex tests
05a66d2c0 support V4 in evex
33017d4fb support V4 in evex
e228e737d prepare evex extension of evex
45eca7987 update doc
98ce73bb2 add cfcmov tests
e2d9685af add cfcmov
a4ec97ca9 add tests of ctestscc
45711c502 add ctestscc
a1f6c14cc add alias of dfv
facb052a1 avoid r15 on 32-bit mode
c1c15848c remove warnings
be319626b add ccmpscc with imm
c4d05037e add ccmpscc
17f7d279c testing ccmpb
ff01b1e20 setcc supports apx
25ceea2ef add 3-op cmovcc
2f8cfb9a8 CMPccXADD supports APX
a9310deac add tests of push/pop
ec2881bfd push/pop support rex2
114152fed add push2/pop2
1aefdb649 support jmpabs
77eca6d0d add tests of 3-op shift
5e54ffdfa add 3-op shift
426814c50 check v instead of r
3f3d6095c disable rol/ror to support NF
ee572b7eb add tests of ror/rol
186d63ad9 add tests of shr/sar
26be71a12 2-op shl supports apx
83f5bd25e remove some warnings
e43d99762 add crc32 tests
92153b6f8 crc32 supports apx
d7ca6a2dd split T_F2 from T_66|T_F3
fb1fc738f tweak
389d73347 movbe supports apx and append test
3636cde22 tests of 1-byte opcode with rex2
1dd020126 check whether or not it is a 1-byte opcode
083822b52 movdiri supports apx
6703d4344 movdir64b supports apx
ed5dc3516 add tests of shld/shrd
b01c0ed40 shld/shrd support apx
c51c4a6f7 add tests of lzcnt and tzcnt
2cc22ea1b lzcnt and tzcnt support apx
baddec288 tweak
1d3a19a50 update doc of apx
273d8d5b6 add 3-op imul with T_zu
50875294c add tests of 2-op imul
d20142d01 add T_zu
eb9de1392 2-op imul supports apx
dba2c174f add 2op neg/not_
95ad5927f add tests of imul/mul/neg/not_ with 1-op
790afb745 add tests o idiv
045ef31a3 add tests of div
1d7e2a6bb div supports apx
e5fe58231 remove warning on 32-bit
66b3a3042 check all regs of NF
c7dba88df add dec test
f55f596ad add inc test
6f6423899 2-op inc/dec
95c0c4e6f tweak inc/dec
f5fda7ace change detection of pp with type
a18e5aeb5 rorx supports apx
5bb8461b4 blsmsk, blsr support apx
a493dc7b4 blsi supports apx
7c1accedc sarx/shlx/shrx support apx and add tests
125d8e740 test bzhi with apx
78be5afd1 add tests of bextr with apx
e9603b79d bextr supports apx
3a85aadc6 pdep, pext support apx
16f1a5d8a mulx supports apx
82529af93 andn supports APX
637ad7a4a add test of NF
e23f5ad75 fix type for adc
1bcc83303 3-op add supports T_nf
5d46b950b the type of all type is uint64_t
0a8ea9edf fix type
b1f0fef4d add test of 3op apx
9b21727ba remove space
6fa1b4a90 reorder of opRO
2d1f229a0 simplify condR
b220be972 simplify opRO
24b71a1ce use Reg instead of Operand if possible
de1353448 rename opGen with opSSE
4cd8e8eac refactor opGpr as opRRO
01d756917 rename
5037120f7 replace old rex with rexA
45fe94fdd rename opLoadSeg2 with opLoadSeg
253f800bc tweak
4f3939d92 rename opModM2 with opModM
fa731a27c rename opModR2 with opModR
e5db7d0e4 rename opModRM2 to opModRM
dc20fd09b use opModRM2
d4da1561b rename opR_ModM2 with opR_ModM
ef3665274 use opR_ModM2
e5b20e5a5 use opModM2
104941db2 use opModM2
6ae769f21 rename opROO2 with opROO
1521cb7ce rename opGen2 to opGen
f9c6cb5dc all opGen are replaced with opGen2
249d6978a use opGen2
81ae48922 use opGen2
b9e4bb2fc always put prefix as byte code
3374a158f use opGen2
719f81f45 use opGen2
8d037ebd6 use opGen2
6f8bc28e2 use opGen2
303876cac use opGen2
f0b49752a rewrite opMovXMM
5d4c48ffd rewrite opMMX
189c3488b use opMMX2
1361d0946 use opMMX2
32cafcc61 tweak
cf1cfd6c4 add temporary converting code
433bf29e3 replacing opModR with opModR2
ba1d07ed1 senduipi uses opModR2
646da9750 use opModR2 for rdrand, rdseed, movq
ccad6cecd use opModR2 for movdq2q, movq2dq
3c21754b9 use opModR2 for movd, movmskps
4718643ef use opModR2 for bswap, maskmovq, pmovmskb
e1a148707 try to use opModR2
220a5def7 split avx_type_def.h in gen/
87b8c8ed2 adox passes the test
bd8477292 fix detection of adox without apx
6b19515eb add adcx, adox with APX
77d6acea6 increase the room of type
710e39bfe add test of r, r/m
ea9cd9ade tweak
057f09c5b rename T_NF to T_nf
57a0c1935 support NF=1
8f49739da remove cmp of 3-op
e3310344c [doc] about APX
cdc2533c1 add test of adc/3op
9c6b81c4d return value on nothrow mode
8d524b4a4 add op(r, r/m, imm) and op(r, r/m, r/m)
4c62d1fdc test adc2(r, op, mem) and adc2(r, mem, op)
6f593a1cb test of adc2 (3op APX)
61addb9d9 simplify opMIB
575c447f1 remove rex2p
a95bd9cc5 add test of adc/add/and_/cmp/or_/sbb/sub/xor_
f7d3c17e8 tweak
d7a7ea912 refactoring rex
acd797139 use opModM instead of opMIB
ad3334ba6 add modRM with rex2
059d115b5 add test of apx.cpp
873c93a51 add test of regs of apx
e25b1cd62 [not tested] add(r1, r2) with rex2
eb118504d remove warning of VC
6c580b1f7 fix cvt test for extended r16-r31
981fa6f05 add r16 - r31
244623812 Merge branch 'dev'
aafe3cb62 build(cmake): bump minimum required to version 3.5
76d7477d7 Merge branch 'dev'
151c8ab04 v6.73
dd66cfb76 add tests of avx-vnni-int{8,16}
4a6132d66 update cpuid list
bea25541a add detection of AVX_VNNI_INT16
d9e76b1c6 add tests of SM4
e1c4c360b add SM4
d79717dbe add tests of SM3
48f8dbeb6 add SM3
5473d3933 vsha512* check regs
9b3687a68 add detection of SHA512, SM3, SM4
ecdd01ee5 mov crypt test in 64-bit mode
c4550b6a9 sde 9.24.0
5762819de add vsha512{msg1, msg2, rnds2}
3255d606a Merge branch 'dev'
322665e72 v6.72
ad178a219 add xabort/xbegin/xend
0924ff4aa Merge branch 'dev'
8980934c1 v6.71
76292b310 add SystemInfo class for win
3e42709ab ignore space and cr
66b2768a6 disable wrong detection of gcc
1855985e1 remove / for mingw64
5bdccc0b8 64bit only for mingw64
33882d0a0 use sysconf(_SC_PAGESIZE) instead of const value 4096 on linux
33075c2bd add link to other projects
60e71402e reorder
79854aa08 add new cpus
5921e270c update cpuid
ce083a0dc Merge branch 'dev'
b538485f3 v6.70
461dd34ee udpate doc
2149c79e3 add test of alias of vpclmulqdq
2c59c5c91 add alias of vpclmulqdq
729ae4aa3 fix alias of pclmulqdq
3c248d68a define XBYAK_CONSTEXPR if XBYAK_ONLY_CLASS_CPU is defined
c0a932d7b Merge remote-tracking branch 'origin/dev'
ef502b5b4 update doc
ba3db4730 update version
c0d7a704f v6.69.2
c535f4737 update cpuid test list
683249232 change the order of args of diff
e81b95583 Merge branch 'Wunkolo-constexpr-typet' into dev
ab3f40587 Allow constexpr TypeT `operator|`
ad5276fa4 Merge pull request #172 from orz--/patch-1
b4d54f6e1 Update changelog.md
58642e0cd Merge branch 'dev'
3b13d068b v6.69.1
d700f6c35 add detection of xsave
740dff2e8 Merge branch 'dev'
dc048a04c v6.69
ad0dfffd2 add senduipi/stui/testui/uiret
e78f1121b add clui
23b40331a add detection of uintr
98a0f1924 remove warning of sign/unsigned
0afd71a27 add detection of SERIALIZE
363bbaa57 sample shows cpu cache info for AMD
edce72709 Cpu supports AMD
git-subtree-dir: externals/xbyak
git-subtree-split: 2ce465bbca46e92dde9c44bbe7940fd7f70e3b97
72 lines
2 KiB
C++
72 lines
2 KiB
C++
#include <assert.h>
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#include "avx_type_def.h"
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const int NONE = 256; // same as Xbyak::CodeGenerator::NONE
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std::string type2String(uint64_t type)
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{
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if (type == 0) return "T_NONE";
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std::string str;
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int low = type & T_NX_MASK;
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if (0 < low && low < 7) {
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const char *tbl[8] = {
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"T_N1", "T_N2", "T_N4", "T_N8", "T_N16", "T_N32"
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};
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assert(low < int(sizeof(tbl) / sizeof(tbl[0])));
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str = tbl[low - 1];
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}
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if (type & T_N_VL) str += "|T_N_VL";
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if (type & T_APX) str += "|T_APX";
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if ((type & T_NX_MASK) == T_DUP) str += "|T_DUP";
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if (type & T_66) str += "|T_66";
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if (type & T_F3) str += "|T_F3";
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if (type & T_F2) str += "|T_F2";
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if (type & T_0F) {
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if (type & T_FP16) {
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str += "|T_MAP5";
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} else {
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str += "|T_0F";
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}
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}
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if (type & T_0F38) {
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if (type & T_FP16) {
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str += "|T_MAP6";
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} else {
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str += "|T_0F38";
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}
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}
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if (type & T_0F3A) str += "|T_0F3A";
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if (type & T_L0) str += "|T_L0";
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if (type & T_L1) str += "|T_L1";
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if (type & T_W0) str += "|T_W0";
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if (type & T_W1) str += "|T_W1";
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if (type & T_EW0) str += "|T_EW0";
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if (type & T_EW1) str += "|T_EW1";
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if (type & T_YMM) str += "|T_YMM";
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if (type & T_EVEX) str += "|T_EVEX";
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if (type & T_ER_X) str += "|T_ER_X";
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if (type & T_ER_Y) str += "|T_ER_Y";
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if (type & T_ER_Z) str += "|T_ER_Z";
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if (type & T_ER_R) str += "|T_ER_R";
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if (type & T_SAE_X) str += "|T_SAE_X";
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if (type & T_SAE_Y) str += "|T_SAE_Y";
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if (type & T_SAE_Z) str += "|T_SAE_Z";
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if (type & T_MUST_EVEX) str += "|T_MUST_EVEX";
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switch (type & T_B16) { // T_B16 = T_B32 | T_B64
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case T_B16: str += "|T_B16"; break;
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case T_B32: str += "|T_B32"; break;
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case T_B64: str += "|T_B64"; break;
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default: break;
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}
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if (type & T_M_K) str += "|T_M_K";
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if (type & T_VSIB) str += "|T_VSIB";
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if (type & T_MEM_EVEX) str += "|T_MEM_EVEX";
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if (type & T_NF) str += "|T_NF";
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if (type & T_CODE1_IF1) str += "|T_CODE1_IF1";
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if (type & T_ND1) str += "|T_ND1";
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if (type & T_ZU) str += "|T_ZU";
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if (str[0] == '|') str = str.substr(1);
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return str;
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}
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