450 lines
13 KiB
C
450 lines
13 KiB
C
/*
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vfp/vfp.h - ARM VFPv3 emulation unit - SoftFloat lib helper
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Copyright (C) 2003 Skyeye Develop Group
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for help please send mail to <skyeye-developer@lists.gro.clinux.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* The following code is derivative from Linux Android kernel vfp
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* floating point support.
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*
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* Copyright (C) 2004 ARM Limited.
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* Written by Deep Blue Solutions Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#pragma once
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#include <cstdio>
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#include "common/common_types.h"
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#include "tests/skyeye_interpreter/skyeye_common/armstate.h"
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#include "tests/skyeye_interpreter/skyeye_common/vfp/asm_vfp.h"
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#define do_div(n, base) {n/=base;}
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enum : u32 {
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FOP_MASK = 0x00b00040,
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FOP_FMAC = 0x00000000,
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FOP_FNMAC = 0x00000040,
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FOP_FMSC = 0x00100000,
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FOP_FNMSC = 0x00100040,
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FOP_FMUL = 0x00200000,
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FOP_FNMUL = 0x00200040,
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FOP_FADD = 0x00300000,
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FOP_FSUB = 0x00300040,
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FOP_FDIV = 0x00800000,
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FOP_EXT = 0x00b00040
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};
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#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
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enum : u32 {
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FEXT_MASK = 0x000f0080,
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FEXT_FCPY = 0x00000000,
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FEXT_FABS = 0x00000080,
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FEXT_FNEG = 0x00010000,
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FEXT_FSQRT = 0x00010080,
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FEXT_FCMP = 0x00040000,
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FEXT_FCMPE = 0x00040080,
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FEXT_FCMPZ = 0x00050000,
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FEXT_FCMPEZ = 0x00050080,
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FEXT_FCVT = 0x00070080,
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FEXT_FUITO = 0x00080000,
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FEXT_FSITO = 0x00080080,
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FEXT_FTOUI = 0x000c0000,
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FEXT_FTOUIZ = 0x000c0080,
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FEXT_FTOSI = 0x000d0000,
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FEXT_FTOSIZ = 0x000d0080
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};
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#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
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#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
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#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
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#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
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#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
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#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
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#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
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#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
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inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
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{
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if (shift) {
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if (shift < 32)
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val = val >> shift | ((val << (32 - shift)) != 0);
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else
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val = val != 0;
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}
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return val;
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}
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inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift)
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{
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if (shift) {
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if (shift < 64)
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val = val >> shift | ((val << (64 - shift)) != 0);
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else
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val = val != 0;
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}
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return val;
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}
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inline u32 vfp_hi64to32jamming(u64 val)
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{
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u32 v;
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u32 highval = val >> 32;
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u32 lowval = val & 0xffffffff;
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if (lowval >= 1)
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v = highval | 1;
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else
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v = highval;
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return v;
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}
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inline void add128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
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{
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*resl = nl + ml;
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*resh = nh + mh;
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if (*resl < nl)
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*resh += 1;
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}
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inline void sub128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
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{
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*resl = nl - ml;
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*resh = nh - mh;
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if (*resl > nl)
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*resh -= 1;
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}
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inline void mul64to128(u64* resh, u64* resl, u64 n, u64 m)
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{
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u32 nh, nl, mh, ml;
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u64 rh, rma, rmb, rl;
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nl = static_cast<u32>(n);
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ml = static_cast<u32>(m);
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rl = (u64)nl * ml;
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nh = n >> 32;
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rma = (u64)nh * ml;
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mh = m >> 32;
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rmb = (u64)nl * mh;
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rma += rmb;
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rh = (u64)nh * mh;
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rh += ((u64)(rma < rmb) << 32) + (rma >> 32);
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rma <<= 32;
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rl += rma;
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rh += (rl < rma);
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*resl = rl;
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*resh = rh;
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}
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inline void shift64left(u64* resh, u64* resl, u64 n)
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{
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*resh = n >> 63;
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*resl = n << 1;
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}
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inline u64 vfp_hi64multiply64(u64 n, u64 m)
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{
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u64 rh, rl;
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mul64to128(&rh, &rl, n, m);
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return rh | (rl != 0);
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}
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inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
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{
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u64 mh, ml, remh, reml, termh, terml, z;
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if (nh >= m)
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return ~0ULL;
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mh = m >> 32;
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if (mh << 32 <= nh) {
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z = 0xffffffff00000000ULL;
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} else {
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z = nh;
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do_div(z, mh);
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z <<= 32;
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}
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mul64to128(&termh, &terml, m, z);
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sub128(&remh, &reml, nh, nl, termh, terml);
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ml = m << 32;
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while ((s64)remh < 0) {
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z -= 0x100000000ULL;
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add128(&remh, &reml, remh, reml, mh, ml);
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}
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remh = (remh << 32) | (reml >> 32);
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if (mh << 32 <= remh) {
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z |= 0xffffffff;
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} else {
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do_div(remh, mh);
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z |= remh;
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}
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return z;
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}
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// Operations on unpacked elements
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#define vfp_sign_negate(sign) (sign ^ 0x8000)
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// Single-precision
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struct vfp_single {
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s16 exponent;
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u16 sign;
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u32 significand;
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};
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// VFP_SINGLE_MANTISSA_BITS - number of bits in the mantissa
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// VFP_SINGLE_EXPONENT_BITS - number of bits in the exponent
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// VFP_SINGLE_LOW_BITS - number of low bits in the unpacked significand
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// which are not propagated to the float upon packing.
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#define VFP_SINGLE_MANTISSA_BITS (23)
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#define VFP_SINGLE_EXPONENT_BITS (8)
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#define VFP_SINGLE_LOW_BITS (32 - VFP_SINGLE_MANTISSA_BITS - 2)
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#define VFP_SINGLE_LOW_BITS_MASK ((1 << VFP_SINGLE_LOW_BITS) - 1)
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// The bit in an unpacked float which indicates that it is a quiet NaN
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#define VFP_SINGLE_SIGNIFICAND_QNAN (1 << (VFP_SINGLE_MANTISSA_BITS - 1 + VFP_SINGLE_LOW_BITS))
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// Operations on packed single-precision numbers
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#define vfp_single_packed_sign(v) ((v) & 0x80000000)
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#define vfp_single_packed_negate(v) ((v) ^ 0x80000000)
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#define vfp_single_packed_abs(v) ((v) & ~0x80000000)
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#define vfp_single_packed_exponent(v) (((v) >> VFP_SINGLE_MANTISSA_BITS) & ((1 << VFP_SINGLE_EXPONENT_BITS) - 1))
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#define vfp_single_packed_mantissa(v) ((v) & ((1 << VFP_SINGLE_MANTISSA_BITS) - 1))
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enum : u32 {
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VFP_NUMBER = (1 << 0),
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VFP_ZERO = (1 << 1),
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VFP_DENORMAL = (1 << 2),
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VFP_INFINITY = (1 << 3),
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VFP_NAN = (1 << 4),
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VFP_NAN_SIGNAL = (1 << 5),
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VFP_QNAN = (VFP_NAN),
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VFP_SNAN = (VFP_NAN|VFP_NAN_SIGNAL)
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};
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inline int vfp_single_type(const vfp_single* s)
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{
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int type = VFP_NUMBER;
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if (s->exponent == 255) {
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if (s->significand == 0)
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type = VFP_INFINITY;
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else if (s->significand & VFP_SINGLE_SIGNIFICAND_QNAN)
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type = VFP_QNAN;
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else
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type = VFP_SNAN;
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} else if (s->exponent == 0) {
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if (s->significand == 0)
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type |= VFP_ZERO;
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else
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type |= VFP_DENORMAL;
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}
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return type;
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}
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// Unpack a single-precision float. Note that this returns the magnitude
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// of the single-precision float mantissa with the 1. if necessary,
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// aligned to bit 30.
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inline void vfp_single_unpack(vfp_single* s, s32 val, u32* fpscr)
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{
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s->sign = vfp_single_packed_sign(val) >> 16,
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s->exponent = vfp_single_packed_exponent(val);
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u32 significand = ((u32)val << (32 - VFP_SINGLE_MANTISSA_BITS)) >> 2;
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if (s->exponent && s->exponent != 255)
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significand |= 0x40000000;
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s->significand = significand;
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// If flush-to-zero mode is enabled, turn the denormal into zero.
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// On a VFPv2 architecture, the sign of the zero is always positive.
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if ((*fpscr & FPSCR_FLUSH_TO_ZERO) != 0 && (vfp_single_type(s) & VFP_DENORMAL) != 0) {
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s->sign = 0;
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s->exponent = 0;
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s->significand = 0;
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*fpscr |= FPSCR_IDC;
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}
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}
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// Re-pack a single-precision float. This assumes that the float is
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// already normalised such that the MSB is bit 30, _not_ bit 31.
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inline s32 vfp_single_pack(const vfp_single* s)
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{
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u32 val = (s->sign << 16) +
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(s->exponent << VFP_SINGLE_MANTISSA_BITS) +
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(s->significand >> VFP_SINGLE_LOW_BITS);
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return (s32)val;
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}
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u32 vfp_single_normaliseround(ARMul_State* state, int sd, vfp_single* vs, u32 fpscr, u32 exceptions, const char* func);
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// Double-precision
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struct vfp_double {
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s16 exponent;
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u16 sign;
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u64 significand;
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};
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// VFP_REG_ZERO is a special register number for vfp_get_double
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// which returns (double)0.0. This is useful for the compare with
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// zero instructions.
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#ifdef CONFIG_VFPv3
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#define VFP_REG_ZERO 32
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#else
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#define VFP_REG_ZERO 16
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#endif
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#define VFP_DOUBLE_MANTISSA_BITS (52)
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#define VFP_DOUBLE_EXPONENT_BITS (11)
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#define VFP_DOUBLE_LOW_BITS (64 - VFP_DOUBLE_MANTISSA_BITS - 2)
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#define VFP_DOUBLE_LOW_BITS_MASK ((1 << VFP_DOUBLE_LOW_BITS) - 1)
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// The bit in an unpacked double which indicates that it is a quiet NaN
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#define VFP_DOUBLE_SIGNIFICAND_QNAN (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1 + VFP_DOUBLE_LOW_BITS))
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// Operations on packed single-precision numbers
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#define vfp_double_packed_sign(v) ((v) & (1ULL << 63))
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#define vfp_double_packed_negate(v) ((v) ^ (1ULL << 63))
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#define vfp_double_packed_abs(v) ((v) & ~(1ULL << 63))
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#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
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#define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
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inline int vfp_double_type(const vfp_double* s)
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{
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int type = VFP_NUMBER;
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if (s->exponent == 2047) {
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if (s->significand == 0)
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type = VFP_INFINITY;
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else if (s->significand & VFP_DOUBLE_SIGNIFICAND_QNAN)
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type = VFP_QNAN;
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else
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type = VFP_SNAN;
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} else if (s->exponent == 0) {
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if (s->significand == 0)
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type |= VFP_ZERO;
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else
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type |= VFP_DENORMAL;
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}
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return type;
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}
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// Unpack a double-precision float. Note that this returns the magnitude
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// of the double-precision float mantissa with the 1. if necessary,
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// aligned to bit 62.
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inline void vfp_double_unpack(vfp_double* s, s64 val, u32* fpscr)
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{
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s->sign = vfp_double_packed_sign(val) >> 48;
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s->exponent = vfp_double_packed_exponent(val);
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u64 significand = ((u64)val << (64 - VFP_DOUBLE_MANTISSA_BITS)) >> 2;
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if (s->exponent && s->exponent != 2047)
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significand |= (1ULL << 62);
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s->significand = significand;
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// If flush-to-zero mode is enabled, turn the denormal into zero.
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// On a VFPv2 architecture, the sign of the zero is always positive.
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if ((*fpscr & FPSCR_FLUSH_TO_ZERO) != 0 && (vfp_double_type(s) & VFP_DENORMAL) != 0) {
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s->sign = 0;
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s->exponent = 0;
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s->significand = 0;
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*fpscr |= FPSCR_IDC;
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}
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}
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// Re-pack a double-precision float. This assumes that the float is
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// already normalised such that the MSB is bit 30, _not_ bit 31.
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inline s64 vfp_double_pack(const vfp_double* s)
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{
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u64 val = ((u64)s->sign << 48) +
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((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) +
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(s->significand >> VFP_DOUBLE_LOW_BITS);
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return (s64)val;
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}
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u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
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// A special flag to tell the normalisation code not to normalise.
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#define VFP_NAN_FLAG 0x100
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// A bit pattern used to indicate the initial (unset) value of the
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// exception mask, in case nothing handles an instruction. This
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// doesn't include the NAN flag, which get masked out before
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// we check for an error.
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#define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG)
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// A flag to tell vfp instruction type.
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// OP_SCALAR - This operation always operates in scalar mode
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// OP_SD - The instruction exceptionally writes to a single precision result.
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// OP_DD - The instruction exceptionally writes to a double precision result.
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// OP_SM - The instruction exceptionally reads from a single precision operand.
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enum : u32 {
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OP_SCALAR = (1 << 0),
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OP_SD = (1 << 1),
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OP_DD = (1 << 1),
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OP_SM = (1 << 2)
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};
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struct op {
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u32 (* const fn)(ARMul_State* state, int dd, int dn, int dm, u32 fpscr);
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u32 flags;
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};
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inline u32 fls(u32 x)
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{
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int r = 32;
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if (!x)
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return 0;
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if (!(x & 0xffff0000u)) {
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x <<= 16;
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r -= 16;
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}
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if (!(x & 0xff000000u)) {
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x <<= 8;
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r -= 8;
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}
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if (!(x & 0xf0000000u)) {
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x <<= 4;
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r -= 4;
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}
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if (!(x & 0xc0000000u)) {
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x <<= 2;
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r -= 2;
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}
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if (!(x & 0x80000000u)) {
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x <<= 1;
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r -= 1;
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}
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return r;
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}
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u32 vfp_double_multiply(vfp_double* vdd, vfp_double* vdn, vfp_double* vdm, u32 fpscr);
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u32 vfp_double_add(vfp_double* vdd, vfp_double* vdn, vfp_double *vdm, u32 fpscr);
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u32 vfp_double_normaliseround(ARMul_State* state, int dd, vfp_double* vd, u32 fpscr, u32 exceptions, const char* func);
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