83 lines
3.1 KiB
C
83 lines
3.1 KiB
C
/*
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* arch/arm/include/asm/vfp.h
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*
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* VFP register definitions.
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* First, the standard VFP set.
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*/
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#pragma once
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// ARM11 MPCore FPSID Information
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// Note that these are used as values and not as flags.
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enum : u32 {
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VFP_FPSID_IMPLMEN = 0x41, // Implementation code. Should be the same as cp15 0 c0 0
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VFP_FPSID_SW = 0, // Software emulation bit value
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VFP_FPSID_SUBARCH = 0x1, // Subarchitecture version number
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VFP_FPSID_PARTNUM = 0x20, // Part number
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VFP_FPSID_VARIANT = 0xB, // Variant number
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VFP_FPSID_REVISION = 0x4 // Revision number
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};
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// FPEXC bits
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enum : u32 {
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FPEXC_EX = (1U << 31U),
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FPEXC_EN = (1 << 30),
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FPEXC_DEX = (1 << 29),
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FPEXC_FP2V = (1 << 28),
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FPEXC_VV = (1 << 27),
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FPEXC_TFV = (1 << 26),
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FPEXC_LENGTH_BIT = (8),
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FPEXC_LENGTH_MASK = (7 << FPEXC_LENGTH_BIT),
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FPEXC_IDF = (1 << 7),
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FPEXC_IXF = (1 << 4),
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FPEXC_UFF = (1 << 3),
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FPEXC_OFF = (1 << 2),
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FPEXC_DZF = (1 << 1),
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FPEXC_IOF = (1 << 0),
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FPEXC_TRAP_MASK = (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
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};
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// FPSCR Flags
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enum : u32 {
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FPSCR_NFLAG = (1U << 31U), // Negative condition flag
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FPSCR_ZFLAG = (1 << 30), // Zero condition flag
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FPSCR_CFLAG = (1 << 29), // Carry condition flag
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FPSCR_VFLAG = (1 << 28), // Overflow condition flag
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FPSCR_QC = (1 << 27), // Cumulative saturation bit
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FPSCR_AHP = (1 << 26), // Alternative half-precision control bit
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FPSCR_DEFAULT_NAN = (1 << 25), // Default NaN mode control bit
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FPSCR_FLUSH_TO_ZERO = (1 << 24), // Flush-to-zero mode control bit
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FPSCR_RMODE_MASK = (3 << 22), // Rounding Mode bit mask
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FPSCR_STRIDE_MASK = (3 << 20), // Vector stride bit mask
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FPSCR_LENGTH_MASK = (7 << 16), // Vector length bit mask
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FPSCR_IDE = (1 << 15), // Input Denormal exception trap enable.
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FPSCR_IXE = (1 << 12), // Inexact exception trap enable
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FPSCR_UFE = (1 << 11), // Undeflow exception trap enable
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FPSCR_OFE = (1 << 10), // Overflow exception trap enable
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FPSCR_DZE = (1 << 9), // Division by Zero exception trap enable
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FPSCR_IOE = (1 << 8), // Invalid Operation exception trap enable
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FPSCR_IDC = (1 << 7), // Input Denormal cumulative exception bit
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FPSCR_IXC = (1 << 4), // Inexact cumulative exception bit
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FPSCR_UFC = (1 << 3), // Undeflow cumulative exception bit
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FPSCR_OFC = (1 << 2), // Overflow cumulative exception bit
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FPSCR_DZC = (1 << 1), // Division by Zero cumulative exception bit
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FPSCR_IOC = (1 << 0), // Invalid Operation cumulative exception bit
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};
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// FPSCR bit offsets
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enum : u32 {
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FPSCR_RMODE_BIT = 22,
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FPSCR_STRIDE_BIT = 20,
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FPSCR_LENGTH_BIT = 16,
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};
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// FPSCR rounding modes
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enum : u32 {
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FPSCR_ROUND_NEAREST = (0 << 22),
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FPSCR_ROUND_PLUSINF = (1 << 22),
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FPSCR_ROUND_MINUSINF = (2 << 22),
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FPSCR_ROUND_TOZERO = (3 << 22)
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};
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