541 lines
23 KiB
C++
541 lines
23 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include <algorithm>
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#include <array>
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#include <cinttypes>
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#include <cstdio>
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#include <cstring>
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#include <functional>
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#include <string_view>
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#include <tuple>
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#include <catch2/catch_test_macros.hpp>
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#include <mcl/bit/bit_field.hpp>
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#include <mcl/stdint.hpp>
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#include "../rand_int.h"
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#include "../unicorn_emu/a32_unicorn.h"
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#include "./testenv.h"
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#include "dynarmic/frontend/A32/FPSCR.h"
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#include "dynarmic/frontend/A32/PSR.h"
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#include "dynarmic/frontend/A32/a32_location_descriptor.h"
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#include "dynarmic/frontend/A32/disassembler/disassembler.h"
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#include "dynarmic/frontend/A32/translate/a32_translate.h"
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#include "dynarmic/interface/A32/a32.h"
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#include "dynarmic/ir/basic_block.h"
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#include "dynarmic/ir/opt/passes.h"
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using namespace Dynarmic;
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static A32::UserConfig GetUserConfig(ThumbTestEnv* testenv) {
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A32::UserConfig user_config;
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user_config.optimizations &= ~OptimizationFlag::FastDispatch;
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user_config.callbacks = testenv;
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return user_config;
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}
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using WriteRecords = std::map<u32, u8>;
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struct ThumbInstGen final {
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public:
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ThumbInstGen(
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std::string_view format, std::function<bool(u32)> is_valid = [](u32) { return true; })
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: is_valid(is_valid) {
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REQUIRE((format.size() == 16 || format.size() == 32));
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const auto bit_size = format.size();
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for (size_t i = 0; i < bit_size; i++) {
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const u32 bit = 1U << (bit_size - 1 - i);
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switch (format[i]) {
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case '0':
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mask |= bit;
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break;
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case '1':
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bits |= bit;
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mask |= bit;
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break;
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default:
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// Do nothing
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break;
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}
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}
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}
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u16 Generate16() const {
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u32 inst;
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do {
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const auto random = RandInt<u16>(0, 0xFFFF);
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inst = bits | (random & ~mask);
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} while (!is_valid(inst));
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ASSERT((inst & mask) == bits);
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return static_cast<u16>(inst);
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}
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u32 Generate32() const {
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u32 inst;
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do {
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const auto random = RandInt<u32>(0, 0xFFFFFFFF);
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inst = bits | (random & ~mask);
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} while (!is_valid(inst));
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ASSERT((inst & mask) == bits);
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return inst;
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}
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private:
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u32 bits = 0;
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u32 mask = 0;
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std::function<bool(u32)> is_valid;
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};
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static bool DoesBehaviorMatch(const A32Unicorn<ThumbTestEnv>& uni, const A32::Jit& jit, const WriteRecords& interp_write_records, const WriteRecords& jit_write_records) {
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const auto interp_regs = uni.GetRegisters();
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const auto jit_regs = jit.Regs();
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return std::equal(interp_regs.begin(), interp_regs.end(), jit_regs.begin(), jit_regs.end()) && uni.GetCpsr() == jit.Cpsr() && interp_write_records == jit_write_records;
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}
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static void RunInstance(size_t run_number, ThumbTestEnv& test_env, A32Unicorn<ThumbTestEnv>& uni, A32::Jit& jit, const ThumbTestEnv::RegisterArray& initial_regs, size_t instruction_count, size_t instructions_to_execute_count) {
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uni.ClearPageCache();
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jit.ClearCache();
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// Setup initial state
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uni.SetCpsr(0x000001F0);
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uni.SetRegisters(initial_regs);
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jit.SetCpsr(0x000001F0);
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jit.Regs() = initial_regs;
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// Run interpreter
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test_env.modified_memory.clear();
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test_env.ticks_left = instructions_to_execute_count;
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uni.SetPC(uni.GetPC() | 1);
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uni.Run();
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const bool uni_code_memory_modified = test_env.code_mem_modified_by_guest;
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const auto interp_write_records = test_env.modified_memory;
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// Run jit
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test_env.code_mem_modified_by_guest = false;
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test_env.modified_memory.clear();
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test_env.ticks_left = instructions_to_execute_count;
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jit.Run();
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const bool jit_code_memory_modified = test_env.code_mem_modified_by_guest;
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const auto jit_write_records = test_env.modified_memory;
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test_env.code_mem_modified_by_guest = false;
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REQUIRE(uni_code_memory_modified == jit_code_memory_modified);
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if (uni_code_memory_modified) {
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return;
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}
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// Compare
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if (!DoesBehaviorMatch(uni, jit, interp_write_records, jit_write_records)) {
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printf("Failed at execution number %zu\n", run_number);
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printf("\nInstruction Listing: \n");
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for (size_t i = 0; i < instruction_count; i++) {
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printf("%04x %s\n", test_env.code_mem[i], A32::DisassembleThumb16(test_env.code_mem[i]).c_str());
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}
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printf("\nInitial Register Listing: \n");
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for (size_t i = 0; i < initial_regs.size(); i++) {
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printf("%4zu: %08x\n", i, initial_regs[i]);
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}
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printf("\nFinal Register Listing: \n");
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printf(" unicorn jit\n");
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const auto uni_registers = uni.GetRegisters();
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for (size_t i = 0; i < uni_registers.size(); i++) {
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printf("%4zu: %08x %08x %s\n", i, uni_registers[i], jit.Regs()[i], uni_registers[i] != jit.Regs()[i] ? "*" : "");
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}
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printf("CPSR: %08x %08x %s\n", uni.GetCpsr(), jit.Cpsr(), uni.GetCpsr() != jit.Cpsr() ? "*" : "");
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printf("\nUnicorn Write Records:\n");
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for (const auto& record : interp_write_records) {
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printf("[%08x] = %02x\n", record.first, record.second);
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}
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printf("\nJIT Write Records:\n");
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for (const auto& record : jit_write_records) {
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printf("[%08x] = %02x\n", record.first, record.second);
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}
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A32::PSR cpsr;
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cpsr.T(true);
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size_t num_insts = 0;
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while (num_insts < instructions_to_execute_count) {
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A32::LocationDescriptor descriptor = {u32(num_insts * 4), cpsr, A32::FPSCR{}};
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IR::Block ir_block = A32::Translate(descriptor, &test_env, {});
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Optimization::NamingPass(ir_block);
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Optimization::A32GetSetElimination(ir_block, {.convert_nz_to_nzc = true});
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Optimization::DeadCodeElimination(ir_block);
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Optimization::A32ConstantMemoryReads(ir_block, &test_env);
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Optimization::ConstantPropagation(ir_block);
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Optimization::DeadCodeElimination(ir_block);
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Optimization::VerificationPass(ir_block);
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printf("\n\nIR:\n%s", IR::DumpBlock(ir_block).c_str());
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printf("\n\nx86_64:\n");
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jit.DumpDisassembly();
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num_insts += ir_block.CycleCount();
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}
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#ifdef _MSC_VER
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__debugbreak();
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#endif
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FAIL();
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}
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}
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void FuzzJitThumb16(const size_t instruction_count, const size_t instructions_to_execute_count, const size_t run_count, const std::function<u16()> instruction_generator) {
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ThumbTestEnv test_env;
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// Prepare memory.
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test_env.code_mem.resize(instruction_count + 1);
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test_env.code_mem.back() = 0xE7FE; // b +#0
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// Prepare test subjects
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A32Unicorn uni{test_env};
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A32::Jit jit{GetUserConfig(&test_env)};
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for (size_t run_number = 0; run_number < run_count; run_number++) {
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ThumbTestEnv::RegisterArray initial_regs;
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std::generate_n(initial_regs.begin(), initial_regs.size() - 1, [] { return RandInt<u32>(0, 0xFFFFFFFF); });
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initial_regs[15] = 0;
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std::generate_n(test_env.code_mem.begin(), instruction_count, instruction_generator);
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RunInstance(run_number, test_env, uni, jit, initial_regs, instruction_count, instructions_to_execute_count);
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}
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}
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void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to_execute_count, const size_t run_count, const std::function<u32()> instruction_generator) {
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ThumbTestEnv test_env;
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// Prepare memory.
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// A Thumb-32 instruction is 32-bits so we multiply our count
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test_env.code_mem.resize(instruction_count * 2 + 1);
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test_env.code_mem.back() = 0xE7FE; // b +#0
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// Prepare test subjects
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A32Unicorn uni{test_env};
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A32::Jit jit{GetUserConfig(&test_env)};
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for (size_t run_number = 0; run_number < run_count; run_number++) {
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ThumbTestEnv::RegisterArray initial_regs;
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std::generate_n(initial_regs.begin(), initial_regs.size() - 1, [] { return RandInt<u32>(0, 0xFFFFFFFF); });
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initial_regs[15] = 0;
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for (size_t i = 0; i < instruction_count; i++) {
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const auto instruction = instruction_generator();
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const auto first_halfword = static_cast<u16>(mcl::bit::get_bits<0, 15>(instruction));
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const auto second_halfword = static_cast<u16>(mcl::bit::get_bits<16, 31>(instruction));
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test_env.code_mem[i * 2 + 0] = second_halfword;
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test_env.code_mem[i * 2 + 1] = first_halfword;
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}
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RunInstance(run_number, test_env, uni, jit, initial_regs, instruction_count, instructions_to_execute_count);
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}
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}
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TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb][Thumb16]") {
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const std::array instructions = {
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ThumbInstGen("00000xxxxxxxxxxx"), // LSL <Rd>, <Rm>, #<imm5>
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ThumbInstGen("00001xxxxxxxxxxx"), // LSR <Rd>, <Rm>, #<imm5>
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ThumbInstGen("00010xxxxxxxxxxx"), // ASR <Rd>, <Rm>, #<imm5>
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ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg
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ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm
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ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm
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ThumbInstGen("010000ooooxxxxxx"), // Data Processing
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ThumbInstGen("010001000hxxxxxx"), // ADD (high registers)
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ThumbInstGen("0100010101xxxxxx", // CMP (high registers)
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[](u32 inst) { return mcl::bit::get_bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE
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ThumbInstGen("0100010110xxxxxx", // CMP (high registers)
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[](u32 inst) { return mcl::bit::get_bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE
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ThumbInstGen("010001100hxxxxxx"), // MOV (high registers)
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ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer
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ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT
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ThumbInstGen("1011101000xxxxxx"), // REV
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ThumbInstGen("1011101001xxxxxx"), // REV16
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ThumbInstGen("1011101011xxxxxx"), // REVSH
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ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #]
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ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm]
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ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #]
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ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset]
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ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #]
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ThumbInstGen("1011010xxxxxxxxx", // PUSH
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[](u32 inst) { return mcl::bit::get_bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
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ThumbInstGen("10111100xxxxxxxx", // POP (P = 0)
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[](u32 inst) { return mcl::bit::get_bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
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ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA
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[](u32 inst) {
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// Ensure that the architecturally undefined case of
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// the base register being within the list isn't hit.
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const u32 rn = mcl::bit::get_bits<8, 10>(inst);
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return (inst & (1U << rn)) == 0 && mcl::bit::get_bits<0, 7>(inst) != 0;
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}),
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// TODO: We should properly test against swapped
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// endianness cases, however Unicorn doesn't
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// expose the intended endianness of a load/store
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// operation to memory through its hooks.
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#if 0
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ThumbInstGen("101101100101x000"), // SETEND
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#endif
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};
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const auto instruction_select = [&]() -> u16 {
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const auto inst_index = RandInt<size_t>(0, instructions.size() - 1);
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return instructions[inst_index].Generate16();
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};
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SECTION("single instructions") {
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FuzzJitThumb16(1, 2, 10000, instruction_select);
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}
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SECTION("short blocks") {
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FuzzJitThumb16(5, 6, 3000, instruction_select);
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}
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// TODO: Test longer blocks when Unicorn can consistently
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// run these without going into an infinite loop.
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#if 0
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SECTION("long blocks") {
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FuzzJitThumb16(1024, 1025, 1000, instruction_select);
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}
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#endif
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}
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TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16]") {
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const std::array instructions = {
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// TODO: We currently can't test BX/BLX as we have
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// no way of preventing the unpredictable
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// condition from occurring with the current interface.
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// (bits zero and one within the specified register
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// must not be address<1:0> == '10'.
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#if 0
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ThumbInstGen("01000111xmmmm000", // BLX/BX
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[](u32 inst){
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const u32 Rm = mcl::bit::get_bits<3, 6>(inst);
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return Rm != 15;
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}),
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#endif
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ThumbInstGen("1010oxxxxxxxxxxx"), // add to pc/sp
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ThumbInstGen("11100xxxxxxxxxxx"), // B
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ThumbInstGen("01000100h0xxxxxx"), // ADD (high registers)
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ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers)
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ThumbInstGen("1101ccccxxxxxxxx", // B<cond>
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[](u32 inst) {
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const u32 c = mcl::bit::get_bits<9, 12>(inst);
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return c < 0b1110; // Don't want SWI or undefined instructions.
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}),
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ThumbInstGen("1011o0i1iiiiinnn"), // CBZ/CBNZ
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ThumbInstGen("10110110011x0xxx"), // CPS
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// TODO: We currently have no control over the generated
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// values when creating new pages, so we can't
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// reliably test this yet.
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#if 0
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ThumbInstGen("10111101xxxxxxxx"), // POP (R = 1)
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#endif
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};
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const auto instruction_select = [&]() -> u16 {
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const auto inst_index = RandInt<size_t>(0, instructions.size() - 1);
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return instructions[inst_index].Generate16();
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};
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FuzzJitThumb16(1, 1, 10000, instruction_select);
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}
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TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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const auto three_reg_not_r15 = [](u32 inst) {
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const auto d = mcl::bit::get_bits<8, 11>(inst);
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const auto m = mcl::bit::get_bits<0, 3>(inst);
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const auto n = mcl::bit::get_bits<16, 19>(inst);
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return d != 15 && m != 15 && n != 15;
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};
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const std::array instructions = {
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ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ
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[](u32 inst) {
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const auto d = mcl::bit::get_bits<8, 11>(inst);
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const auto m = mcl::bit::get_bits<0, 3>(inst);
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const auto n = mcl::bit::get_bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd0001mmmm", // QADD8
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0001mmmm", // QADD16
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd0001mmmm", // QASX
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB
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three_reg_not_r15),
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ThumbInstGen("111110101110nnnn1111dddd0001mmmm", // QSAX
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd1010mmmm", // QSUB
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three_reg_not_r15),
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ThumbInstGen("111110101100nnnn1111dddd0001mmmm", // QSUB8
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three_reg_not_r15),
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ThumbInstGen("111110101101nnnn1111dddd0001mmmm", // QSUB16
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT
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[](u32 inst) {
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const auto d = mcl::bit::get_bits<8, 11>(inst);
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const auto m = mcl::bit::get_bits<0, 3>(inst);
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const auto n = mcl::bit::get_bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101001nnnn1111dddd1000mmmm", // REV
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[](u32 inst) {
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const auto d = mcl::bit::get_bits<8, 11>(inst);
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const auto m = mcl::bit::get_bits<0, 3>(inst);
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const auto n = mcl::bit::get_bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101001nnnn1111dddd1001mmmm", // REV16
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[](u32 inst) {
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const auto d = mcl::bit::get_bits<8, 11>(inst);
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const auto m = mcl::bit::get_bits<0, 3>(inst);
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const auto n = mcl::bit::get_bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101001nnnn1111dddd1011mmmm", // REVSH
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[](u32 inst) {
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const auto d = mcl::bit::get_bits<8, 11>(inst);
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const auto m = mcl::bit::get_bits<0, 3>(inst);
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const auto n = mcl::bit::get_bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
|
|
}),
|
|
ThumbInstGen("111110101000nnnn1111dddd0000mmmm", // SADD8
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101001nnnn1111dddd0000mmmm", // SADD16
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101010nnnn1111dddd0000mmmm", // SASX
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101000nnnn1111dddd0010mmmm", // SHADD8
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101001nnnn1111dddd0010mmmm", // SHADD16
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101010nnnn1111dddd0010mmmm", // SHASX
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101110nnnn1111dddd0010mmmm", // SHSAX
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101100nnnn1111dddd0010mmmm", // SHSUB8
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101101nnnn1111dddd0010mmmm", // SHSUB16
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101101nnnn1111dddd0000mmmm", // SSUB16
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101000nnnn1111dddd0100mmmm", // UADD8
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101000nnnn1111dddd0110mmmm", // UHADD8
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101001nnnn1111dddd0110mmmm", // UHADD16
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101010nnnn1111dddd0110mmmm", // UHASX
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101110nnnn1111dddd0110mmmm", // UHSAX
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101100nnnn1111dddd0110mmmm", // UHSUB8
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101101nnnn1111dddd0110mmmm", // UHSUB16
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101010nnnn1111dddd0101mmmm", // UQASX
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101110nnnn1111dddd0101mmmm", // UQSAX
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101100nnnn1111dddd0101mmmm", // UQSUB8
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101101nnnn1111dddd0101mmmm", // UQSUB16
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101100nnnn1111dddd0100mmmm", // USUB8
|
|
three_reg_not_r15),
|
|
ThumbInstGen("111110101101nnnn1111dddd0100mmmm", // USUB16
|
|
three_reg_not_r15),
|
|
};
|
|
|
|
const auto instruction_select = [&]() -> u32 {
|
|
const auto inst_index = RandInt<size_t>(0, instructions.size() - 1);
|
|
|
|
return instructions[inst_index].Generate32();
|
|
};
|
|
|
|
SECTION("single instructions") {
|
|
FuzzJitThumb32(1, 2, 10000, instruction_select);
|
|
}
|
|
|
|
SECTION("short blocks") {
|
|
FuzzJitThumb32(5, 6, 3000, instruction_select);
|
|
}
|
|
}
|
|
|
|
TEST_CASE("Verify fix for off by one error in MemoryRead32 worked", "[Thumb][Thumb16]") {
|
|
ThumbTestEnv test_env;
|
|
|
|
// Prepare test subjects
|
|
A32Unicorn<ThumbTestEnv> uni{test_env};
|
|
A32::Jit jit{GetUserConfig(&test_env)};
|
|
|
|
constexpr ThumbTestEnv::RegisterArray initial_regs{
|
|
0xe90ecd70,
|
|
0x3e3b73c3,
|
|
0x571616f9,
|
|
0x0b1ef45a,
|
|
0xb3a829f2,
|
|
0x915a7a6a,
|
|
0x579c38f4,
|
|
0xd9ffe391,
|
|
0x55b6682b,
|
|
0x458d8f37,
|
|
0x8f3eb3dc,
|
|
0xe18c0e7d,
|
|
0x6752657a,
|
|
0x00001766,
|
|
0xdbbf23e3,
|
|
0x00000000,
|
|
};
|
|
|
|
test_env.code_mem = {
|
|
0x40B8, // lsls r0, r7, #0
|
|
0x01CA, // lsls r2, r1, #7
|
|
0x83A1, // strh r1, [r4, #28]
|
|
0x708A, // strb r2, [r1, #2]
|
|
0xBCC4, // pop {r2, r6, r7}
|
|
0xE7FE, // b +#0
|
|
};
|
|
|
|
RunInstance(1, test_env, uni, jit, initial_regs, 5, 5);
|
|
}
|