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640ce48baa
VFP: Implement {Get,Set}ExtendedRegister{32,64}
2016-08-05 18:54:19 +0100
d31bbd6d14
Common/x64/CpuDetect: Disable MSVC warning for strncpy
2016-08-05 18:42:26 +0100
4c0a85f3b3
EmitX64: Correct EmitPack2x32To1x64 implementation
2016-08-05 18:41:25 +0100
742eeb8913
BackendX64/RegAlloc: Correct debugging asserts and correct UseDef behaviour for spill locations
2016-08-05 18:40:28 +0100
d2aeb56503
Common: DEBUG_ASSERTs weren't enabled
2016-08-05 18:39:47 +0100
6f6f60c61b
tests/FuzzArm: Only call raise(SIGTRAP) when __unix__ is defined
2016-08-05 16:04:16 +0100
d80dcc5367
BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64
2016-08-05 15:27:29 +0100
2b025183a2
BackendX64/RegAlloc: Correct UseDefRegsiter behaviour for last use
2016-08-05 15:24:25 +0100
b4aa01ccf4
Merge remote-tracking branch 'tilkax/master'
2016-08-05 14:13:09 +0100
94e75ad32f
BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg}
2016-08-05 14:11:27 +0100
92bd5f214b
BackendX64/RegAlloc: Add RegisterAddDef, UseDefOpArg, UseOpArg
2016-08-05 14:10:39 +0100
01cfaf0286
IR: Properly support Identity in IR::Value
2016-08-05 14:09:10 +0100
ca40015145
IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
2016-08-05 14:07:27 +0100
fce8c86c90
Implement RSB
2016-08-05 02:13:26 +0100
eb2e6e8bea
Implement some multiplies
2016-08-05 02:03:23 +0100
72c503016c
Fix Pack2x32To1x64
2016-08-05 01:57:43 +0100
3fdc093d10
Add more IR opcodes for multiply instructions
2016-08-04 22:04:42 +0100
a97668ead4
Simplify ARM fuzz tests
2016-08-05 01:56:35 +0100
023643b4fa
Disable load/store tests for now
2016-08-05 02:07:09 +0100
ab383b4be5
Break tests by fixing them
2016-08-05 01:51:35 +0100
af27ef8d6c
Optionally disassemble x86_64 code using LLVM
2016-08-05 01:50:31 +0100
39563c8ea8
Merged in bunnei/dynarmic (pull request #8 )
2016-08-04 13:22:00 +0100
691e4139fa
arm: Implement B/BL/BX instructions.
2016-08-02 19:52:17 -0400
fc33f1d374
Implement more instructions
2016-08-02 10:16:30 +0100
30a90295b9
Implement data processing instructions
2016-08-03 00:44:35 +0100
fe71cc9d78
Disassemble reg-shifted regs in lower case
2016-07-31 19:09:25 +0100
2488926341
Add IR opcode RotateRightExtended
2016-07-31 19:07:35 +0100
dacaeadb6a
Raise SIGTRAP on non-Windows
2016-07-31 19:03:52 +0100
306e070ab5
Use opcodes.inc for emit_x64.h
2016-07-31 14:52:28 +0100
61eddbd1fa
Fix Linux build
2016-07-30 23:58:02 +0100
1252bd653d
RegAlloc: Define constructors for HostLocInfo to make MSVC happy
2016-08-03 00:25:42 +0100
a875c0c720
TranslateArm: Stub more ARM instructions
2016-08-02 21:59:33 +0100
64c17a2489
tests/FuzzArm: Print out IR upon failure
2016-08-02 13:48:06 +0100
deb5e2c10d
IR::DumpBlock: Incorrect use of std::map::at
2016-08-02 13:47:05 +0100
4414ec5bc8
RegAlloc: Allow allocation of XMM registers
2016-08-02 13:46:12 +0100
864081d1a0
BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR
2016-08-02 12:00:11 +0100
6097a21955
TranslateArm: Reorganisation - Split visitor into multiple .cpp files
2016-08-01 20:20:22 +0100
93af160c97
arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface
2016-08-01 20:03:13 +0100
be87038ffd
IROpt: Port get/set elimination pass to current IR
2016-08-02 11:51:05 +0100
e60cea3a54
Add -pedantic-errors compilation flag
2016-08-01 19:54:31 +0100
cd86ef4236
Add -DBOOST_POOL_NO_MT as a compiler flag
2016-07-23 05:37:07 +0100
51448aa06d
More Speed
2016-07-22 23:55:00 +0100
5fbfc6c155
Implement some simple IR optimizations (get/set eliminiation and DCE)
2016-07-21 21:48:45 +0100
90d317b868
Implement memory endianness. Implement Thumb SETEND instruction.
2016-07-20 15:34:17 +0100
98bd7ff6a5
Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support.
2016-07-20 12:08:17 +0100
95316b8443
Merged in Subv/dynarmic/arm_mem_tests (pull request #4 )
2016-07-20 10:19:55 +0100
95588d3faa
Fix Thumb BLX (imm), BL (imm) for negative immediates
2016-07-18 22:48:23 +0100
3f11a149d7
Implement Thumb Instructions: BLX (imm), BL (imm)
2016-07-18 22:18:58 +0100
fce8f75077
Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC.
2016-07-18 16:13:33 -0500
426ffc9971
Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH.
2016-07-18 16:13:02 -0500
c330d9e0e3
Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests.
2016-07-18 16:10:35 -0500
e0d6e28b67
Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)
2016-07-18 21:04:39 +0100
ccc61472b9
Added format strings for ARM STRBT encodings A1 and A2
2016-07-18 14:20:58 -0500
8617bf80a1
Added format strings for ARM LDRBT encodings A1 and A2
2016-07-18 14:18:39 -0500
5d5ea9325c
Added format strings for ARM STRT encodings A1 and A2
2016-07-18 14:05:53 -0500
2363759c62
Implement thumb STM, LDM. Fix thumb POP implementation for P=1.
2016-07-18 20:05:35 +0100
8a310777a1
backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC
2016-07-18 20:01:48 +0100
77761ba032
Added the format strings for LDRT encodings A1 and A2.
2016-07-18 14:01:18 -0500
14dcb18bbe
Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2)
2016-07-18 18:48:08 +0100
a605a43ef9
Implement Thumb Instructions: STRH (imm), LDRH (imm)
2016-07-18 18:28:52 +0100
f9755870bb
Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg)
2016-07-18 18:01:15 +0100
3b8790bf29
Merged in Subv/dynarmic/small_opt (pull request #3 )
2016-07-18 17:38:12 +0100
dfef65d98f
Implement thumb POP instruction
2016-07-18 17:37:48 +0100
703a46ec99
Pass the current IR::Block by reference to the emitter.
2016-07-18 11:27:33 -0500
f7e3d7b8d2
Implement Thumb PUSH instruction
2016-07-18 15:11:16 +0100
9109b226af
Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm)
2016-07-18 11:16:12 +0100
c18a3eeab4
Better MSVC support
2016-07-18 10:28:17 +0100
bf99ddd065
Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic
2016-07-18 10:33:52 +0100
28a201da16
Implement Thumb ADR instruction
2016-07-18 09:25:33 +0100
6708960aeb
Merged in Subv/dynarmic/rev (pull request #2 )
2016-07-17 22:13:36 +0100
0cdf5fe751
Implemented ARM REV and REVSH instructions, with tests.
2016-07-17 14:45:42 -0500
24aa24b1bc
Merged in Subv/dynarmic (pull request #1 )
2016-07-17 19:43:49 +0100
7f09510945
Implemented ARM CMP (imm) instruction.
2016-07-17 13:29:37 -0500
3720da4e19
Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
2016-07-16 19:23:42 +0100
866dce0f23
tests/Thumb: Add revsh (thumb) test
2016-07-16 19:22:57 +0100
22b1bd7cc7
tests/Skyeye: Fix thumb REVSH translation
2016-07-16 19:22:09 +0100
3ef9da9a92
Docs: Design documentation
2016-07-15 16:47:13 +0100
4b1c27e64f
Implement arm_ADC_imm
2016-07-14 20:02:41 +0100
63242924fc
Implement thumb16_SVC
2016-07-14 15:01:30 +0100
181f78f36e
Common: Remove src/common/logging/log.*
2016-07-14 14:55:08 +0100
07eaf100ba
Reorganise src/frontend: Add subdirectories disassembler and translate
2016-07-14 14:39:43 +0100
9b2aff166a
Implement arm_SVC
2016-07-14 14:04:43 +0100
672ffb93d0
frontend/translator: Skeleton for Arm translator
2016-07-14 13:28:20 +0100
7d7751c157
Allow IR blocks to require a cond for block entry.
2016-07-14 12:52:53 +0100
4ab4ca58f9
backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight
2016-07-14 09:02:27 +0100
08e848044d
backend_x64: Inline Routines::GenReturnFromRunCode into emitted code
2016-07-12 16:46:27 +0100
619b451902
clang support
2016-07-12 14:31:43 +0100
8449deb0bc
MSVC support
2016-07-12 13:25:33 +0100
44352680c6
s/thumb1/thumb16/g: Thumb16 refers to 16-bit thumb instructions, and Thumb32 to 32-bit ones
2016-07-12 11:09:34 +0100
6e46e7899a
Translate/Thumb: Fallback to interpreter for Thumb32 instructions
2016-07-12 11:02:45 +0100
60455f9bbc
tests/fuzz_thumb: Fuzz instructions that may change the PC
2016-07-12 10:58:57 +0100
09420d190b
IR: Implement IR microinstructions ALUWritePC and LoadWritePC
2016-07-12 10:58:14 +0100
65d27f3486
tests: Add some Arm tests
2016-07-12 09:12:56 +0100
f85b86486b
frontend/TranslateArm: Just interpret all ARM instructions
2016-07-12 09:04:47 +0100
1410221b47
Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
2016-07-11 23:06:35 +0100
e7922e4fef
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
2016-07-11 22:43:53 +0100
cbcf61a9e6
backend_x64/RegAlloc: Provide convenience function HostCall to save registers necessary as per host ABI
2016-07-11 15:28:10 +0100
d92a771e3c
tests/fuzz_thumb: Implement verification of memory writes
2016-07-10 13:29:15 +0800
f0f14fa5e8
Implement thumb1_MOV_reg
2016-07-10 13:10:06 +0800
8920ce79b9
Implement thumb_CMP_reg_t2
2016-07-10 12:23:16 +0800
MerryMage
Tillmann Karras
bunnei
Subv