suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity
649 commits 2 branches 0 tags 34 MiB
Commit graph

136 commits

Author SHA1 Message Date
MerryMage
c09e69bb97 A64: Implement addsub instructions 2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0 A64: Implement ADD_shifted 2020-04-22 20:42:44 +01:00
MerryMage
e161cf16f5 A64: Initial framework 2020-04-22 20:42:44 +01:00
MerryMage
f61da0b5a9 IR: Compile-time type-checking of IR 2020-04-22 20:39:27 +01:00
MerryMage
44f7f04b5c IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg 2020-04-22 20:39:27 +01:00
MerryMage
9d15e0a8e1 Final A32 refactor 2020-04-22 20:39:27 +01:00
MerryMage
8bef20c24d IR: Split off A32 specific opcodes 2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278 A32: Split off A32 specific IREmitter 2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622 Label A32 specific code appropriately 2020-04-22 20:33:30 +01:00
MerryMage
19a7fb8992 jit_state: Split off CPSR.NZCV 2020-04-22 20:26:40 +01:00
MerryMage
311361b409 jit_state: Split off CPSR.{E,T} 
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
 2020-04-22 20:26:40 +01:00
MerryMage
cb119c2f72 emit_x64: Use boost::icl::interval_map to speed up ranged invalidation 2020-04-22 20:26:40 +01:00
MerryMage
7cac9519b0 microinstruction: Remove DecrementRemainingUses 2020-04-22 20:26:12 +01:00
MerryMage
5d72f7048f basic_block: Add inst address and use count to DumpBlock 
This additional output assists with debugging.
 2020-04-22 20:26:12 +01:00
MerryMage
d1e0a29cd9 Implement IR instruction PackedSelect, reimplement SEL 2020-04-22 20:26:07 +01:00
MerryMage
814e378249 VCMP and VCMPE were the other way around 
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
 2020-04-22 20:26:07 +01:00
MerryMage
29471be317 Standardize location of storage-class specifiers: Place at beginning of declarations 
Justification: C99 specifies that doing otherwise is an obsolescent feature.
 2017-09-29 01:23:45 +01:00
MerryMage
523ae542f4 microinstruction: Implement HasAssociatedPseudoOperation 2017-04-04 13:10:50 +01:00
MerryMage
05e97058c3 parallel: Add and Subtract with Exchange improvements 
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
 2017-03-24 15:56:24 +00:00
Lynn
fd068ed6b8 Ranged cache invalidation 2017-03-20 11:58:25 +00:00
MerryMage
92a01b0cd8 Prefer ASSERT to DEBUG_ASSERT 2017-02-26 23:30:40 +00:00
MerryMage
bbeea72eba ir_opt: Remove redundant shift instructions 2017-02-26 15:28:14 +00:00
MerryMage
4ed8ee7489 microinstruction: Void arguments when invalidating instruction 2017-02-18 21:29:23 +00:00
MerryMage
642ccb0f66 ir/value: Support U16 immediates 2017-01-29 22:58:11 +00:00
MerryMage
5f7ffe0d0b microinstruction: Implement Inst::AreAllArgsImmediates 2017-01-29 22:56:59 +00:00
MerryMage
22804dc6a5 microinstruction: Arguments of Inst::Use and Inst::UndoUse should be const 2017-01-29 22:53:46 +00:00
MerryMage
1d4446cad5 microinstruction: Removed unnecessary reference from argument of Inst::ReplaceUsesWith 2017-01-29 22:52:33 +00:00
MerryMage
48693eb6ff Implement coprocessor-related microinstructions 
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
 2017-01-08 14:56:06 +00:00
MerryMage
d8a37e287c IR: Add IR type CoprocInfo 2017-01-08 14:56:06 +00:00
MerryMage
1efd3a764d IR: Remove unused microinstructions NegateLowWord and NegateHighWord 2017-01-05 20:16:39 +00:00
FernandoS27
d5610eb26c Implement UHASX, UHSAX, SHASX and SHSAX (#75) 2016-12-28 21:32:22 +00:00
Fernando Sahmkow
677f62dd6f Implement SHSUB8 and SHSUB16 (#74) 
* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
 2016-12-22 12:02:24 +00:00
MerryMage
6a269a6ebd IR: Add microinstructions UnsignedSaturation and SignedSaturation 2016-12-21 19:51:25 +00:00
FernandoS27
8919265d2c Implement SADD8, SADD16, SSUB8, SSUB16, USUB16 2016-12-20 21:52:38 +00:00
FernandoS27
3f6ecfe245 Implemented USAD8 and USADA8 2016-12-20 21:52:38 +00:00
MerryMage
96e46ba6b5 Implement QADD, QSUB, QDADD, QDSUB 2016-12-15 22:34:29 +00:00
MerryMage
52e1445f43 Implement USUB8 2016-12-05 00:29:15 +00:00
MerryMage
5c1aab1666 Implement CLZ 
Includes tests
 2016-12-04 22:56:33 +00:00
MerryMage
1a1646d962 Implement UADD8 2016-12-04 20:52:33 +00:00
MerryMage
7cad6949e7 IR: Implement new pseudo-operation GetGEFromOp 2016-12-04 20:52:06 +00:00
MerryMage
e166965f3e Implement VCMP 2016-12-03 11:41:09 +00:00
MerryMage
f2fe376fc6 Support 64-bit immediates 2016-12-03 11:29:50 +00:00
Mat M
de1f831d79 microinstruction: Make use_count private (#53) 
Makes the operation a part of the direct interface.
 2016-11-30 21:51:06 +00:00
Merry
0ff8c375af Implement UHSUB8 and UHSUB16 (#48) 2016-11-26 18:27:21 +00:00
Merry
cb17f9a3ed Implement SHADD8 and SHADD16 (#47) 2016-11-26 18:12:29 +00:00
MerryMage
c0c1bb1094 Implemented UHADD16 2016-11-26 11:28:20 +00:00
Yuri Kunde Schlesner
9ec51f74bd libfmt: Update version to current master 2016-11-25 20:47:04 +00:00
Sebastian Valle
4d44474ad4 Implemented the ARM UHADD8 instruction. (#45) 
The x64 implementation uses the SSSE3 instruction PSHUFB.
A non-SSE fallback is provided in case the CPU doesn't support it.
 2016-11-25 20:32:22 +00:00
MerryMage
b6f7b8babd ir: Implement GetGEFlags, SetGEFlags 2016-11-23 19:44:27 +00:00
Mat M
6a2174ebfa Add missing explicit specifiers (#27) 2016-09-07 12:08:48 +01:00