suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity
3434 commits 2 branches 0 tags 34 MiB
Commit graph

3434 commits

This branch
This branch
All branches
Author SHA1 Message Date
MerryMage
d31bbd6d14 Common/x64/CpuDetect: Disable MSVC warning for strncpy 2016-08-05 18:44:01 +01:00
MerryMage
4c0a85f3b3 EmitX64: Correct EmitPack2x32To1x64 implementation 2016-08-05 18:43:24 +01:00
MerryMage
742eeb8913 BackendX64/RegAlloc: Correct debugging asserts and correct UseDef behaviour for spill locations 2016-08-05 18:43:22 +01:00
MerryMage
d2aeb56503 Common: DEBUG_ASSERTs weren't enabled 2016-08-05 18:43:21 +01:00
MerryMage
6f6f60c61b tests/FuzzArm: Only call raise(SIGTRAP) when __unix__ is defined 2016-08-05 16:04:16 +01:00
MerryMage
d80dcc5367 BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64 2016-08-05 15:27:29 +01:00
MerryMage
2b025183a2 BackendX64/RegAlloc: Correct UseDefRegsiter behaviour for last use 2016-08-05 15:24:25 +01:00
MerryMage
b4aa01ccf4 Merge remote-tracking branch 'tilkax/master' 2016-08-05 14:14:06 +01:00
MerryMage
94e75ad32f BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg} 2016-08-05 14:11:27 +01:00
MerryMage
92bd5f214b BackendX64/RegAlloc: Add RegisterAddDef, UseDefOpArg, UseOpArg 2016-08-05 14:10:39 +01:00
MerryMage
01cfaf0286 IR: Properly support Identity in IR::Value 2016-08-05 14:09:10 +01:00
MerryMage
ca40015145 IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint) 2016-08-05 14:07:27 +01:00
Tillmann Karras
fce8c86c90 Implement RSB 
somehow missed this earlier
 2016-08-05 02:13:26 +01:00
Tillmann Karras
eb2e6e8bea Implement some multiplies 2016-08-05 02:09:54 +01:00
Tillmann Karras
72c503016c Fix Pack2x32To1x64 
Not sure how to fix this properly.
 2016-08-05 02:09:30 +01:00
Tillmann Karras
3fdc093d10 Add more IR opcodes for multiply instructions 
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
 2016-08-05 02:09:30 +01:00
Tillmann Karras
a97668ead4 Simplify ARM fuzz tests 2016-08-05 02:09:30 +01:00
Tillmann Karras
023643b4fa Disable load/store tests for now 
I don't feel like debugging that right now.
 2016-08-05 02:09:27 +01:00
Tillmann Karras
ab383b4be5 Break tests by fixing them 2016-08-05 02:08:41 +01:00
Tillmann Karras
af27ef8d6c Optionally disassemble x86_64 code using LLVM 2016-08-05 02:08:41 +01:00
Merry
39563c8ea8 Merged in bunnei/dynarmic (pull request #8) 
arm: Implement B/BL/BX instructions.
 2016-08-04 13:22:00 +01:00
bunnei
691e4139fa arm: Implement B/BL/BX instructions. 2016-08-03 16:49:01 -04:00
Tillmann Karras
fc33f1d374 Implement more instructions 
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
 2016-08-03 00:47:17 +01:00
Tillmann Karras
30a90295b9 Implement data processing instructions 
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST

The code could use some serious deduplication...
 2016-08-03 00:47:16 +01:00
Tillmann Karras
fe71cc9d78 Disassemble reg-shifted regs in lower case 2016-08-03 00:47:16 +01:00
Tillmann Karras
2488926341 Add IR opcode RotateRightExtended 
to rotate through the carry flag
 2016-08-03 00:47:16 +01:00
Tillmann Karras
dacaeadb6a Raise SIGTRAP on non-Windows 2016-08-03 00:44:08 +01:00
Tillmann Karras
306e070ab5 Use opcodes.inc for emit_x64.h 2016-08-03 00:44:08 +01:00
Tillmann Karras
61eddbd1fa Fix Linux build 2016-08-03 00:44:08 +01:00
MerryMage
1252bd653d RegAlloc: Define constructors for HostLocInfo to make MSVC happy 2016-08-03 00:25:42 +01:00
MerryMage
a875c0c720 TranslateArm: Stub more ARM instructions 2016-08-02 21:59:33 +01:00
MerryMage
64c17a2489 tests/FuzzArm: Print out IR upon failure 2016-08-02 13:48:06 +01:00
MerryMage
deb5e2c10d IR::DumpBlock: Incorrect use of std::map::at 2016-08-02 13:47:05 +01:00
MerryMage
4414ec5bc8 RegAlloc: Allow allocation of XMM registers 2016-08-02 13:46:12 +01:00
MerryMage
864081d1a0 BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR 2016-08-02 12:00:11 +01:00
MerryMage
6097a21955 TranslateArm: Reorganisation - Split visitor into multiple .cpp files 2016-08-02 11:54:04 +01:00
MerryMage
93af160c97 arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface 2016-08-02 11:54:02 +01:00
MerryMage
be87038ffd IROpt: Port get/set elimination pass to current IR 2016-08-02 11:51:05 +01:00
MerryMage
e60cea3a54 Add -pedantic-errors compilation flag 2016-08-01 19:54:31 +01:00
MerryMage
cd86ef4236 Add -DBOOST_POOL_NO_MT as a compiler flag 2016-07-23 05:37:07 +01:00
MerryMage
51448aa06d More Speed 2016-07-22 23:55:00 +01:00
MerryMage
5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) 2016-07-21 21:48:45 +01:00
MerryMage
90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage
98bd7ff6a5 Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support. 2016-07-20 12:08:17 +01:00
Merry
95316b8443 Merged in Subv/dynarmic/arm_mem_tests (pull request #4) 
Added some fuzz tests for most cases of ARM Load/Store instructions
 2016-07-20 10:19:55 +01:00
MerryMage
95588d3faa Fix Thumb BLX (imm), BL (imm) for negative immediates 2016-07-18 22:48:23 +01:00
MerryMage
3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) 2016-07-18 22:18:58 +01:00
Subv
fce8f75077 Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC. 2016-07-18 16:13:33 -05:00
Subv
426ffc9971 Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH. 
These tests do not test the behavior of writing to the PC.
 2016-07-18 16:13:02 -05:00
Subv
c330d9e0e3 Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests. 2016-07-18 16:10:35 -05:00